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Analysis of hardware implementations of deblocking filter for video codecs

机译：视频编解码器去块滤波器硬件实现分析

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摘要

H.264 and H.265 are the most popular video coding standards used for various applications. These coding standards use multiple modules to perform video compression. Among the various modules, the deblocking filter (DBF) is one of the critical modules in the video codec, which requires extensive computation. It is computationally complicated and critically time-consuming. DBF removes the blocking artefacts caused due to inverse transform, intra-prediction, inter-frame prediction and motion compensated prediction. For the past two decades, the deblocking filtering algorithm is implemented in hardware and research is still going on for realising optimised hardware solutions for this critical module. Efficient hardware implementation of the DBF is essential for high-resolution video applications such as HDTV to increase the decoding throughput, to achieve high speed and to reduce the off-chip memory access cycles. This paper presents an intricate analysis of various hardware architectures of DBF used for H.264 and H.265 coding standards.
机译：H.264和H.265是用于各种应用的最受欢迎的视频编码标准。这些编码标准使用多个模块来执行视频压缩。在各种模块中，去块滤波器（DBF）是视频编解码器中的临界模块之一，这需要广泛的计算。它是计算方式复杂且令人疑虑的耗时。 DBF去除由于逆变换，帧内预测，​​帧间预测和运动补偿预测而引起的阻塞人工制品。在过去的二十年中，在硬件中实现了去块滤波算法，研究仍在实现该关键模块的优化硬件解决方案。 DBF的高效硬件实现对于高分辨率视频应用，例如HDTV增加解码吞吐量，以实现高速并减少片外存储器访问周期。本文介绍了用于H.264和H.265编码标准的DBF各种硬件架构的复杂分析。

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