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首页> 外文期刊>International journal of mobile network design and innovation >An enhanced architecture for pattern matching in FPGA for intrusion detection in wireless sensor networks
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An enhanced architecture for pattern matching in FPGA for intrusion detection in wireless sensor networks

机译：用于FPGA中模式匹配的增强架构，用于无线传感器网络中的入侵检测

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摘要

Due to increasing number of network worms and virus, network users are vulnerable to malicious attacks. A network intrusion detection system (NIDS) provides an effective security solution. It monitors network traffic for suspicious data patterns, and informs system administrators to take proper actions. Implementing NIDS in WSNs have unique constraints as compared to traditional networks making the implementation of existing security measures impracticable due to limitation in data memory, code space and energy to power the sensor. In this paper, a novel FPGA-based signature match co-processor structural design is proposed. The computational complexity of our proposed bitmap encoder based NIDS is compared with ROM based NIDS. Experimental results show that the proposed architecture due to the reduction in the hardware leads to an efficient reduction in the size of the sensor nodes, increases the speed of the network and decreases the power consumption of the WSN.
机译：由于网络蠕虫和病毒数量的增加，网络用户容易受到恶意攻击。网络入侵检测系统（NIDS）提供了有效的安全解决方案。它监视网络流量中可疑的数据模式，并通知系统管理员采取适当的措施。与传统网络相比，在WSN中实现NIDS具有独特的约束，由于数据存储器，代码空间和为传感器供电的能量有限，因此无法实施现有的安全措施。本文提出了一种新颖的基于FPGA的签名匹配协处理器结构设计。将我们提出的基于位图编码器的NIDS与基于ROM的NIDS的计算复杂度进行了比较。实验结果表明，由于减少了硬件，所提出的体系结构有效地减少了传感器节点的大小，提高了网络速度，并降低了WSN的功耗。

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