Multifingers Capacitances Modeling of 65-Nm CMOS Transistor by Unit Cell Method

Alit Apriyana Anak Agung; Yue Ping Zhang

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Multifingers Capacitances Modeling of 65-Nm CMOS Transistor by Unit Cell Method

机译：基于单元法的65 Nm CMOS晶体管多指电容建模

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The multifingers' parasitic capacitances modeling of 65-nm CMOS transistors for millimeter-wave application is presented. The modeling is based on simulation approach, which is done by building the devices true dimension in high-frequency structure simulator environment. The material properties of the devices as given by the foundry are used dur-ing simulation and then full electromagnetic simulations are carried out to extract the Y-pa-rameters of the model. Unit-cell parameters extraction method is carried out in order to save memory and simulation time. In this case, the multifinger transistors are divided into unit-cells and then the parasitic capacitances of the unit-cells are calculated from the extracted Y-parameter. Based on linear scaling, the parasitic capacitance of the multifingers transistor can be obtained with good accuracy (less than 5% error).

机译：提出了毫米波应用的65 nm CMOS晶体管的多指寄生电容模型。建模基于仿真方法，通过在高频结构仿真器环境中构建设备的真实尺寸来完成。在仿真过程中使用了铸造厂给出的设备的材料特性，然后进行了完整的电磁仿真，以提取模型的Y参数。为了节省内存和仿真时间，执行了单元参数提取方法。在这种情况下，将多指晶体管划分为单位单元，然后根据提取的Y参数来计算单位单元的寄生电容。基于线性缩放，可以以良好的精度（小于5％的误差）获得多指晶体管的寄生电容。

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来源
《International journal of RF and microwave computer-aided engineering》 |2012年第3期|p.297-307|共11页
作者
Alit Apriyana Anak Agung; Yue Ping Zhang;
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作者单位

Virtus IC Design Centre, Nanyang Technological University, Nanyang Ave, Singapore 639798;

Division of Circuits and Systems, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639789;

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正文语种 eng
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关键词
CMOS; millimeter-wave integrated circuit; SPST switch; HFSS; unit-cell;

机译：CMOS;毫米波集成电路;SPST开关;HFSS;单位单元;

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Multifingers Capacitances Modeling of 65-Nm CMOS Transistor by Unit Cell Method

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