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首页> 外文期刊>International journal of systems,control and communications >Dual-scan architecture for 2D discrete wavelet transform using modified lifting algorithm
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Dual-scan architecture for 2D discrete wavelet transform using modified lifting algorithm

机译：使用修改提升算法的2D离散小波变换的双扫描架构

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摘要

An efficient architecture of discrete wavelet transform (DWT) in two-dimension (2D) is presented in this paper. The proposed structure has a higher hardware efficiency and better performance than the other DWT structures. The conventional lifting scheme is modified to reduce the latency and critical path to one multiplier delay (1 T_(m) ). The processing speed of the architecture is increased by introducing four pipeline stages in the DWT structure. Cohen-Daubechies-Feauveau (CDF) 9/7 wavelet filter is implemented in the paper. The data scanning of the input image for processing is done in Z -fashion. The computation time of an N × N image is N ~(2)/2 and the temporal buffer requirement is 4 N . The DWT architecture developed based on the modified lifting scheme has a regular data flow with a throughput rate of two. Very high speed hardware description language (VHDL) is used to describe the digital design. The architecture is implemented on CADENCE tool with CMOS 180 nm technology. The results after comparison indicate that the proposed architecture is hardware efficient and memory utilisation is reasonable as a result of which this structure can be used in real-time image and video compression.
机译：本文提出了两维（2D）中的离散小波变换（DWT）的有效架构。所提出的结构具有更高的硬件效率和比其他DWT结构更好的性能。修改传统提升方案以降低一个乘法延迟的延迟和临界路径（1 T_（m））。通过在DWT结构中引入四个管道阶段来增加架构的处理速度。 Cohen-Daubechies-Feaureau（CDF）9/7小波过滤器是在纸上实施的。用于处理的输入图像的数据扫描在Z-Fashion中完成。 n×n图像的计算时间是n〜（2）/ 2，并且时间缓冲器要求是4 n。基于改进的提升方案开发的DWT架构具有常规数据流，其吞吐率为2。非常高速硬件描述语言（VHDL）用于描述数字设计。该架构在具有CMOS 180 NM技术的Cadence工具上实现。比较后的结果表明，所提出的架构是硬件有效，并且内存利用是合理的，因此该结构可以用于实时图像和视频压缩。

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