Impacts of Surface Roughness Reduction in (110) Si Substrates Fabricated by High-Temperature Annealing on Electron Mobility in n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors on (110) Si

Sung-Ho Jeon; Noriyuki Taoka; Hiroaki Matsumoto; Kiyotaka Nakano; Susumu Koyama; Hiroshi Kakibayasi; Koji Araki; Moriya Miyashita; Koji Izunome; Mitsuru Takenaka; Shinichi Takagi

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Impacts of Surface Roughness Reduction in (110) Si Substrates Fabricated by High-Temperature Annealing on Electron Mobility in n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors on (110) Si

机译：高温退火降低（110）Si衬底表面粗糙度对（110）Si上n沟道金属氧化物半导体场效应晶体管中电子迁移率的影响

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The effects of high-temperature Ar/H_2 annealing on (110) Si, which is known to provide flat (110) Si surfaces, have been studied from the viewpoint of metal-oxide-semiconductor (MOS) interface roughness and inversion-layer electron mobility limited by surface roughness scattering in (110) Si n-channel metal-oxide-semiconductor field-effect transistors (n-MOSFETs). It has been confirmed by quantitative transmission electron microscope (TEM) analysis that the reduction in the surface roughness on (110) Si is still maintained after gate oxidation with gate oxide thickness (T_(ox)) of 6.9nm. The mobility measurement of (110) Si n-MOSFETs fabricated using Si wafers with high-temperature Ar/H_2 annealing has revealed that the high-temperature annealing Increases the electron mobility of (110) Si MOSFETs at 10 K by 14 and 5.7% for T_(ox) values of 6.9 and 8.9 nm, respectively, and increases the electron mobility at 300 K by 2.5 and 0.72% for T_(ox) values of 6.9 and 8.9 nm, respectively. The T_(ox) dependence of the enhancement factor might be attributable to the increase in MOS interface roughness with increasing T_(ox). It has also been observed that the mobility enhancement factor is slightly dependent on the channel direction. The mobility increase has been observed to be greater along (111) than along (112).

机译：从金属氧化物半导体（MOS）界面粗糙度和反型层电子的角度研究了高温Ar / H_2退火对已知提供（110）Si表面的（110）Si的影响迁移率受到（110）Si n沟道金属氧化物半导体场效应晶体管（n-MOSFET）中表面粗糙度散射的限制。通过定量透射电子显微镜（TEM）分析已经确认，在以6.9nm的栅极氧化物厚度（T_（ox））进行栅极氧化之后，仍然保持（110）Si上的表面粗糙度的降低。使用具有高温Ar / H_2退火的Si晶片制造的（110）Si n-MOSFET的迁移率测量结果表明，高温退火使（110）Si MOSFET在10 K时的电子迁移率分别提高了14和5.7％。 T_（ox）值分别为6.9和8.9 nm，并且对于T_（ox）值分别为6.9和8.9 nm，在300 K下的电子迁移率分别提高了2.5和0.72％。增强因子的T_（ox）依赖性可能归因于MOS界面粗糙度随T_（ox）的增加而增加。还已经观察到，迁移率增强因子稍微取决于信道方向。已经观察到沿着（111）的迁移率增加比沿着（112）的迁移率增加更大。

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《Japanese journal of applied physics》 |2013年第4issue2期|04CC26.1-04CC26.5|共5页
作者
Sung-Ho Jeon; Noriyuki Taoka; Hiroaki Matsumoto; Kiyotaka Nakano; Susumu Koyama; Hiroshi Kakibayasi; Koji Araki; Moriya Miyashita; Koji Izunome; Mitsuru Takenaka; Shinichi Takagi;
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Department of Electrical Engineering and Information Systems, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan;

Department of Electrical Engineering and Information Systems, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan,Department of Crystalline Materials Science, Nagoya University, Nagoya 464-8603, Japan;

Hitachi High-Technologies Corporation, Hitachinaka, Ibaraki 312-0057, Japan;

Hitachi High-Technologies Corporation, Hitachinaka, Ibaraki 312-0057, Japan;

Hitachi High-Technologies Corporation, Hitachinaka, Ibaraki 312-0057, Japan;

Hitachi High-Technologies Corporation, Hitachinaka, Ibaraki 312-0057, Japan;

Covalent Silicon Corporation, Seiro, Niigata 957-0197, Japan;

Covalent Silicon Corporation, Seiro, Niigata 957-0197, Japan;

Covalent Silicon Corporation, Seiro, Niigata 957-0197, Japan;

Department of Electrical Engineering and Information Systems, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan;

Department of Electrical Engineering and Information Systems, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan;

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Impacts of Surface Roughness Reduction in (110) Si Substrates Fabricated by High-Temperature Annealing on Electron Mobility in n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors on (110) Si

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