Gate Overlap Optimization and Performance Variation for Thin-Film Transistors with Source/Drain Edge Waviness

Jaewook Jeong; Yongtaek Hong

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Gate Overlap Optimization and Performance Variation for Thin-Film Transistors with Source/Drain Edge Waviness

机译：具有源极/漏极边缘波纹度的薄膜晶体管的栅极重叠优化和性能变化

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By using ATLAS three-dimensional (3D) device simulator, we analyzed influence of gate overlap (GO) between gate and source/drain (S/D) electrodes on channel current and parasitic resistance variations of bottom-gate staggered thin-film transistors (TFTs) with wavy edge S/D electrodes that are frequently observed due to printing process variation, especially for narrow line printing. Transmission line method (TLM) analysis was performed, and showed channel current variation had a significant dependency on gate overlap. As gate overlap increases, current flow becomes less localized around peaks of the wavy edge pattern, reducing parasitic resistance. However, reduction of parasitic resistance becomes saturated when gate overlap is greater than the lateral distance over which current is collected by the contact of the wavy edge TFT. This lateral distance was found to be smaller than peak-to-peak magnitude of the wavy patterns.

机译：通过使用ATLAS三维（3D）器件仿真器，我们分析了栅极与源极/漏极（S / D）电极之间的栅极重叠（GO）对底栅交错薄膜晶体管的沟道电流和寄生电阻变化的影响（带有波浪形边缘S / D电极的TFT）由于印刷工艺的变化而经常被观察到，特别是对于窄线印刷。进行了传输线方法（TLM）分析，结果表明沟道电流变化对栅极重叠有很大的依赖性。随着栅极重叠的增加，电流在波形边缘图案的峰值附近变得越来越不集中，从而降低了寄生电阻。然而，当栅极重叠大于通过波浪形边缘TFT的接触收集电流的横向距离时，寄生电阻的减小变得饱和。发现该横向距离小于波浪图案的峰峰值。

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《Japanese journal of applied physics》 |2010年第3issue1期|p.036501.1-036501.5|共5页
作者
Jaewook Jeong; Yongtaek Hong;
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Department of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-9 dong, Gwanak-gu, Seoul 151-744, Korea;

Department of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-9 dong, Gwanak-gu, Seoul 151-744, Korea;

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1. Analysis of effective channel length variation for thin-film transistors with edge waviness in source/drain electrodes [J] . Jaewook Jeong, Yongtaek Hong Thin Solid Films . 2010,第22期

机译：源/漏电极中具有边缘波纹的薄膜晶体管的有效沟道长度变化分析
2. A novel thin-film transistor with step gate-overlapped lightly doped drain and raised source/drain design [J] . Chien Feng-Tso, Chen Jian-Liang, Chen Chien-Ming, Solid-State Electronics . 2017,第nova期

机译：一种新颖的薄膜晶体管，具有阶梯式栅极重叠的轻掺杂漏极和凸起的源极/漏极设计
3. Modelling and numerical analysis for wavy edge in printed source and drain electrodes of thin-film transistors [J] . J. Jeong, Y. Hong, S.H. Baek, Electronics Letters . 2008,第10期

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4. Asymmetric Conductance of Oxide Thin-Film Transistors Induced by Top-Gate Effect of Drain Overlap Capacitance [C] . Hongtao Huang, Qin Zhang, Chao Dai, International Conference on Display Technology;Society for Information Display . -1

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Gate Overlap Optimization and Performance Variation for Thin-Film Transistors with Source/Drain Edge Waviness

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