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首页> 外文期刊>Japanese journal of applied physics >Nanoscale Two-Bit/Cell NAND Silicon-Oxide-Nitride-Oxide-Silicon Devices Designed on Fully Depleted Silicon-on-Insulator Substrates
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Nanoscale Two-Bit/Cell NAND Silicon-Oxide-Nitride-Oxide-Silicon Devices Designed on Fully Depleted Silicon-on-Insulator Substrates

机译：在完全耗尽的绝缘体上硅衬底上设计的纳米级两比特/单元NAND氧化硅-氮化物-氧化硅硅器件

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摘要

Nanoscale 2-bit/cell NAND silicon-oxide-nitride-oxide-si|icon (SONOS) memory devices with two separated control gates utilizing a fully depleted silicon-on-insulator (SOI) structure were designed. The program and erase characteristics of the proposed unique nanoscale 2-bit/cell NAND SONOS memory devices were simulated using technology computer-aided design tools. Simulation results showed that the leakage current in the subthreshold region and trie subthreshold swing for the nanoscale 2-bit/cell NAND SONOS memory devices were decreased by utilizing a SOI structure. The initial threshold voltage of the nanoscale 2-bit/cell NAND SONOS memory devices with a SOI structure was larger than that of conventional SONOS devices without a SOI structure, indicative of a decrease in leakage current. Simulation results showed that the short-channel effects in the nanoscale 2-bit/cell NAND SONOS memory devices decreased in magnitude owing to a larger effective channel length.
机译：设计了利用两个完全耗尽的绝缘体上硅（SOI）结构，具有两个分离的控制栅极的纳米级2位/单元NAND氧化硅-氮化物-氧化硅（SONOS）存储设备。拟议的独特纳米级2位/单元NAND SONOS存储设备的编程和擦除特性是使用计算机辅助设计技术进行仿真的。仿真结果表明，通过利用SOI结构，纳米级2位/单元NAND SONOS存储器件的亚阈值区域和三亚阈值摆幅的泄漏电流得以减小。具有SOI结构的纳米级2位/单元NAND SONOS存储器件的初始阈值电压大于不具有SOI结构的常规SONOS器件的初始阈值电压，表明泄漏电流减小。仿真结果表明，由于更大的有效通道长度，纳米级2位/单元NAND SONOS存储设备中的短通道效应在大小上有所降低。

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  • 来源
    《Japanese journal of applied physics》 |2010年第9issue1期|p.094201.1-094201.4|共4页
  • 作者

    Hyun Joo Kim; Joo Hyung You; Kae Dal Kwack; Tae Whan Kim;

  • 作者单位

    Department of Information Display Engineering, Hanyang University, Seoul 133-791, Korea;

    rnDepartment of Electronics and Computer Engineering, Hanyang University, Seoul 133-791, Korea;

    rnDepartment of Information Display Engineering, Hanyang University, Seoul 133-791, Korea Department of Electronics and Computer Engineering, Hanyang University, Seoul 133-791, Korea;

    rnDepartment of Information Display Engineering, Hanyang University, Seoul 133-791, Korea Department of Electronics and Computer Engineering, Hanyang University, Seoul 133-791, Korea;

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