Self-heating-aware cell design for p-vertically-integrated nanowire on FinFET beyond 3 nm technology node

Yamagishi Tomohiko; Hori Atsushi; Muneta Lriya; Kakushima Kuniyuki; Tsutsui Kazuo; Wakabayashi Hitoshi

首页> 外文期刊>Japanese journal of applied physics >Self-heating-aware cell design for p-vertically-integrated nanowire on FinFET beyond 3 nm technology node

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Self-heating-aware cell design for p-vertically-integrated nanowire on FinFET beyond 3 nm technology node

机译：超过3 nm技术节点的FinFET上的P / N垂直集成纳米线的自热感知单元设计

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Self-heating-aware design for pin-vertically-integrated nanowire (NW) on FinFET is investigated for beyond 3 nm technology node. The practical fabrication process architecture for nanowires on FinFET has been also proposed. Based on the assumptions of process flow, cell layouts for inverter, transmission gate, NAND, NOR and 6TLSRAM are designed. Consequently, remarkable area reductions are achieved for various CMOS circuits including multi-stacked circuits resulting in the suppression of the self-heating effect simultaneously. (C) 2020 The Japan Society of Applied Physics.

机译：对FINFET上的针垂直集成纳米线（NW）的自热感知设计进行了研究，以超过3nm技术节点。还提出了FinFET上纳米线的实用制造过程架构。基于过程流动的假设，设计了用于逆变器，传输门，NAND和和6TLSRAM的单元格布局。因此，对于包括多堆叠电路的各种CMOS电路实现了显着的区域减少，导致同时抑制自加热效果。（c）2020日本应用物理学会。

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《Japanese journal of applied physics》 |2020年第sg期|SGGA09.1-SGGA09.7|共7页
作者
Yamagishi Tomohiko; Hori Atsushi; Muneta Lriya; Kakushima Kuniyuki; Tsutsui Kazuo; Wakabayashi Hitoshi;
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Tokyo Inst Technol Midori Ku 4259 Nagatsuta Cho Yokohama Kanagawa 2268502 Japan;

Tokyo Inst Technol Midori Ku 4259 Nagatsuta Cho Yokohama Kanagawa 2268502 Japan;

Tokyo Inst Technol Midori Ku 4259 Nagatsuta Cho Yokohama Kanagawa 2268502 Japan;

Tokyo Inst Technol Midori Ku 4259 Nagatsuta Cho Yokohama Kanagawa 2268502 Japan;

Tokyo Inst Technol Midori Ku 4259 Nagatsuta Cho Yokohama Kanagawa 2268502 Japan;

Tokyo Inst Technol Midori Ku 4259 Nagatsuta Cho Yokohama Kanagawa 2268502 Japan;

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1. Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm Node SOI FinFET Technology [J] . Xingsheng Wang, Binjie Cheng, Kuang J.B., Design & Test,IEEE . 2014,第6期

机译：统计可变性和可靠性以及对14nm节点SOI FinFET技术的相应6T-SRAM单元设计的影响
2. Design and analysis of SOI and SELBOX junctionless FinFET at sub-15 nm technology node [J] . Singh Satya Prakash, Akram Waseem Indian journal of engineering and materials sciences . 2020,第5期

机译：SUS-15 NM技术节点SOI和SELBOX连接FINFET的设计与分析
3. Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL) [J] . Seongjae Cho, Jung Hoon Lee, Shinichi Ouchi, Solid-State Electronics . 2010,第10期

机译：考虑栅极感应的漏极泄漏（GIDL）的低待机功耗（LSTP）操作的32 nm技术节点上的SOI FinFET设计
4. FinFET/nanowire design for 5nm/3nm technology nodes: Channel cladding and introducing a “bottleneck” shape to remove performance bottleneck [C] . Victor Moroz, Joanne Huang, Munkang Choi IEEE Electron Devices Technology and Manufacturing Conference . 2017

机译：FINFET /纳米线设计为5nm / 3nm技术节点：通道包层和引入“瓶颈”形状，以去除性能瓶颈
5. Static Random-Access Memory Designs Based on Different Finfets at Lower Technology Node (7NM) [D] . Nizam, Athiya . 2019

机译：基于较低技术节点（7nm）的不同FINFET的静态随机存取存储器设计
6. Novel 14-nm Scallop-Shaped FinFETs (S-FinFETs) on Bulk-Si Substrate [O] . Weijia Xu, Huaxiang Yin, Xiaolong Ma, 2015

机译：体硅衬底上的新型14nm扇贝形FinFET（S-FinFET）
7. Simulation Study of Multiple FIN FinFET Design for 32nm Technology Node and Beyond [O] . Edited T. Grasser, S. Selberherr September, Xinlin Wang, 2014

机译：32nm技术节点及其超宽带多FIN FinFET设计仿真研究

Self-heating-aware cell design for p-vertically-integrated nanowire on FinFET beyond 3 nm technology node

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