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Fast Multi-precision Multiplication for Public-Key Cryptography on Embedded Microprocessors

机译:嵌入式微处理器上公钥加密的快速多精度乘法

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Multi-precision multiplication is one of the most fundamental operations on microprocessors to allow public-key cryptography such as RSA and elliptic curve cryptography. In this paper, we present a novel multiplication technique that increases the performance of multiplication by sophisticated caching of operands. Our method significantly reduces the number of neededloadinstructions which is usually one of the most expensive operations on modern processors. We evaluate our new technique on an 8-b ATmega128 and a 32-b ARM7TDMI microcontroller and compare the results with existing solutions. For the ATmega128, our implementation needs only 2395 clock cycles for a 160-b multiplication. The number of requiredloadinstructions is reduced from 167 (needed for the best known hybrid multiplication) to only 80. On the ARM7TDMI, our implementation needs only 281 clock cycles as opposed to 357. For both platforms, the proposed technique outperforms related work by a factor of about 10-23%. We also show that the method scales very well even for larger integer sizes (required for RSA) and limited register sets. It fully complies with existing multiply-accumulate instructions that are integrated in most of the available processors.
机译:多精度乘法是微处理器上最基本的操作之一,以允许RSA和椭圆曲线加密等公钥加密。在本文中,我们提出了一种新型乘法技术,通过复杂的操作数来增加乘法的性能。我们的方法显着降低了所需手段的数量,通常是现代处理器上最昂贵的操作之一。我们在8-B ATMEGA128和32-B ARM7TDMI微控制器上评估我们的新技术,并将结果与​​现有解决方案进行比较。对于Atmega128,我们的实现仅需要2395个时钟周期,用于160-B倍增。从167(最可知的混合乘法所需)减少了所需LOUDIONINGS的数量,仅为80.在ARM7TDMI上,我们的实现仅需要281个时钟周期,而不是357.对于这两个平台,所提出的技术通过一个因素优于相关的工作约10-23%。我们还表明,即使对于较大的整数大小(RSA所需)和有限寄存器集,该方法也非常稳定。它完全符合现有的乘法累积指令,这些指令集成在大多数可用处理器中。

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