An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

Patrick Girard; Olivier Héron; Serge Pravossoudovitch; Michel Renovell

首页> 外文期刊>Journal of Electronic Testing >An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

【24h】

An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

机译：基于对称SRAM的FPGA逻辑单元中延迟故障的高效BIST架构

获取原文

获取原文并翻译 | 示例

掌桥外文数据库（机构版） >>

开具论文收录证明 >>

文献代查 >>

页面导航

摘要
著录项
相似文献
相关主题

摘要

The objective of this paper is to propose a BIST scheme enabling the test of delay faults in all the Look-Up Tables (LUTs) of FPGA SRAMs, in a Manufacturing context. The BIST scheme does not consume any area overhead and can be removed from the device after the test thus, allowing the use of the whole circuit by the user. The structure we propose is composed of a simple test pattern generator, an error detector and a chain of LUTs. The chain of LUTs is formed alternatively by a LUT and a flip–flop. By using such a chain, the test of all delay faults in every LUT is enabled. In this paper, we develop an experiment based on the implantation of our BIST architecture in a Virtex FPGA from Xilinx. The purpose of this experiment is to show the feasibility of our solution. As a result, one important issue from this solution is its ability to detect the “smallest” delay faults in the LUTs, i.e. the smallest delays that can be observed on a LUT output.

机译：本文的目的是提出一种BIST方案，该方案能够在制造环境中测试FPGA SRAM的所有查找表（LUT）中的延迟故障。 BIST方案不消耗任何面积开销，并且可以在测试后从器件中移除，从而允许用户使用整个电路。我们提出的结构由一个简单的测试模式生成器，一个错误检测器和一系列LUT组成。 LUT链由LUT和触发器交替形成。通过使用这样的链，可以测试每个LUT中的所有延迟故障。在本文中，我们基于在Xilinx的Virtex FPGA中植入BIST架构而开发了一个实验。此实验的目的是证明我们解决方案的可行性。结果，该解决方案的一个重要问题是其检测LUT中“最小”延迟故障的能力，即在LUT输出上可以观察到的最小延迟。

著录项

来源
《Journal of Electronic Testing》 |2006年第2期|161-172|共12页
作者
Patrick Girard; Olivier Héron; Serge Pravossoudovitch; Michel Renovell;
展开▼
作者单位

Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier Université Montpellier II/CNRS (UMR 5506);

Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier Université Montpellier II/CNRS (UMR 5506);

Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier Université Montpellier II/CNRS (UMR 5506);

Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier Université Montpellier II/CNRS (UMR 5506);

展开▼
收录信息
原文格式 PDF
正文语种 eng
中图分类
关键词
BIST; delay faults; look-up table;

机译：BIST;延迟故障;查找表;

相似文献

外文文献
中文文献
专利

1. An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs [J] . PATRICK GIRARD, OLIVIER HERON, SERGE PRAVOSSOUDOVITCH, Journal of Electronic Testing: Theory and Applications: Theory and Applications . 2006,第2期

机译：基于对称SRAM的FPGA逻辑单元中延迟故障的高效BIST架构
2. PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era [J] . Zahra Ebrahimi, Behnam Khaleghi, Hossein Asadi IEEE Transactions on Computers . 2017,第6期

机译：PEAF：黑暗硅时代使用可重配置硬逻辑设计的基于SRAM的FPGA的高能效架构
3. Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs [J] . PATRICK GIRARD, OLIVIER HERON, SERGE PRAVOSSOUDOVITCH, Journal of Electronic Testing: Theory and Applications: Theory and Applications . 2005,第1期

机译：在基于SRAM的FPGA中查找表的延迟故障测试
4. BIST of delay faults in the logic architecture of symmetrical FPGAs [C] . Girard, P., Heron, . 2004

机译：对称FPGA逻辑架构中的延迟故障的BIST
5. Hardware and Software Fault-Tolerance of Softcore Processors Implemented in SRAM-Based FPGAs [D] . Rollins, Nathaniel H. 2012

机译：基于SRAM的FPGA中实现的软核处理器的硬件和软件容错
6. Cs-Symmetric Triphenylamine-LinkedBisthiazole-Based Metal-Free Donor–Acceptor Organic Dye for Efficient ZnO Nanoparticles-BasedDye-Sensitized Solar Cells: Synthesis Theoretical Studies and PhotovoltaicProperties [O] . Ramesh Maragani, §, Mohammad Shaad Ansari, 2017

机译：Cs-对称三苯胺连接高效基于ZnO纳米粒子的基于联苯并唑的无金属供体-受体有机染料染料敏化太阳能电池：合成理论研究和光伏性质
7. BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs [O] . Patrick Girard, Olivier Héron, Serge Pravossoudovitch, 2014

机译：对称FpGa逻辑体系结构中延迟故障的BIsT

An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

摘要

著录项

相似文献

相关主题

期刊订阅