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首页> 外文期刊>Journal of interconnection networks >PARALLEL GAUSS-SEIDEL ON A TORUS NETWORK-ON-CHIP ARCHITECTURE
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PARALLEL GAUSS-SEIDEL ON A TORUS NETWORK-ON-CHIP ARCHITECTURE

机译:圆片式网络体系结构上的并行高斯-赛德尔

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Network-on-chip multicore architectures with a large number of processing elements are becoming a reality with the recent developments in technology. In these modern systems the processing elements are interconnected with regular network-on-chip (NoC) topologies such as meshes and trees. In this paper we propose a parallel Gauss-Seidel (GS) iterative algorithm for solving large systems of linear equations on a torus NoC architecture. The proposed parallel algorithm is O(Nn~2 /κ~2 ) time complexity for solving a system with matrix of order n on a κ × κ torus NoC architecture with N iterations assuming n and N are large compared to κ (i.e. for large linear systems that require a large number of iterations). We show that under these conditions the proposed parallel GS algorithm has near optimal speedup.
机译:随着技术的最新发展,具有大量处理元件的片上网络多核架构已成为现实。在这些现代系统中,处理元素与常规的片上网络(NoC)拓扑(例如网格和树)互连。在本文中,我们提出了一种并行的高斯-赛德尔(GS)迭代算法,用于求解Torus NoC架构上的大型线性方程组。所提出的并行算法是O(Nn〜2 /κ〜2)时间复杂度,用于解决κ×κ圆环NoC架构上具有n阶矩阵的系统,并假设n和N比κ大(即,对于n需要大量迭代的线性系统)。我们表明,在这些条件下,提出的并行GS算法具有接近最佳的加速比。

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