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Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip

机译：片上网络上可重配置的数据并行恒定几何快速傅里叶变换架构

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摘要

This paper reports the design and development of reconfigurable (up to 8192-point), data parallel, constant geometry fast Fourier transform (CG-FFT) architectures based on Network-on-Chip (NoC) paradigm. Twiddle factor multiplications have been realized using pipelined CORDIC rotators in the proposed architecture in order to ensure its high throughput. Mapping of FFT functions to cores has been done by considering the proposed signal flow graph (SFG) for CG-FFT architecture, which helps in optimizing the design of network components (routers and network interfaces) and reducing the latency of FFT computation. The proposed input-size aware architecture can withstand faults in other processing elements (PEs) as it can accomplish the entire FFT computation using only one PE as well. When mapped onto mesh based NoC, the proposed architectures could achieve reduction in latency by 5 x, compared to several existing, FFT architectures on NoC. Hardware realization of the PE and the network components of the proposed architectures have been done using Xilinx Kintex-7 family field-programmable gate array (FPGA) device. The maximum operating frequency of a PE in the proposed architecture has been found to be 184.010 MHz, which meets the timing specifications of several application standards, such as DVB-T/H, DAB, 802.11a and UWB. In addition to the FPGA-prototype, the proposed architectures have also been synthesized in ASIC design flow to obtain area and power results. (C) 2015 Elsevier B.V. All rights reserved.
机译：本文报告了基于片上网络（NoC）范式的可重配置（最多8192点），数据并行，恒定几何快速傅里叶变换（CG-FFT）架构的设计和开发。为了确保高吞吐量，在建议的体系结构中使用流水线式的CORDIC旋转器实现了旋转因子乘法。通过考虑为CG-FFT体系结构提议的信号流图（SFG），已经完成了FFT功能到核心的映射，这有助于优化网络组件（路由器和网络接口）的设计并减少FFT计算的延迟。所提出的输入大小感知体系结构可以承受其他处理元件（PE）的故障，因为它也可以仅使用一个PE来完成整个FFT计算。与基于NoC的几种现有FFT架构相比，将其映射到基于网状的NoC时，所提出的架构可以将延迟降低5倍。使用Xilinx Kintex-7系列现场可编程门阵列（FPGA）器件完成了PE和所提出架构的网络组件的硬件实现。已经发现，在所提出的体系结构中，PE的最大工作频率为184.010 MHz，它满足几种应用标准的时序规范，例如DVB-T / H，DAB，802.11a / n和UWB。除FPGA原型外，所提出的架构也已在ASIC设计流程中进行了综合，以获得面积和功耗结果。 （C）2015 Elsevier B.V.保留所有权利。

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