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首页> 外文期刊>Journal of Low Power Electronics >Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture
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Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture

机译：可扩展且高效节能，可动态重新配置的快速傅立叶变换架构

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摘要

Fast Fourier Transform is an integral part of OFDM systems. FFT is the most compute intensive operation that critically affects the OFDM system performance. In order to support the various OFDM standards, a scalable and reconfigurable FFT architecture is necessary. This paper presents an energy efficient and scalable FFT architecture, which can be dynamically reconfigured to adapt to specifications of different standards. The proposed architecture is based on Radix-4~n algorithm and uses a parallel-pipelined unrolled architecture. The proposed architecture can be scaled to support FFTs of sizes upto 64 K points. As a proof of concept, FFT architecture for computation of FFTs of sizes 64 to 4096 point has been implemented in UMC 65 nm 1P10M CMOS process with a maximum clock frequency of 125 MHz and area of 1.05 mm~2. The power consumption at 40 MHz is 33.5 mW for the computation of 4096 point FFT. Energy efficiency (FFTs per unit of energy) of the proposed architecture is 1176 for 1 K point, 584 for 2 K point and 291 for 4 K point FFTs at 40 MHz. The proposed architecture shows better performance in terms of scalability and energy efficiency when compared to existing implementations.
机译：快速傅立叶变换是OFDM系统不可或缺的一部分。 FFT是计算量最大的运算，会严重影响OFDM系统的性能。为了支持各种OFDM标准，可伸缩和可重新配置的FFT体系结构是必要的。本文提出了一种节能高效且可扩展的FFT架构，可以对其进行动态重新配置以适应不同标准的规范。所提出的架构基于Radix-4〜n算法，并使用了并行流水线展开架构。所提议的体系结构可以缩放以支持大小高达64 K点的FFT。作为概念证明，在UMC 65 nm 1P10M CMOS工艺中实现了用于计算64至4096点大小FFT的FFT体系结构，最大时钟频率为125 MHz，面积为1.05 mm〜2。对于4096点FFT的计算，在40 MHz时的功耗为33.5 mW。所提出架构的能量效率（每单位能量FFT）在40 MHz下对于1 K点为1176，对于2 K点为584，对于4 K点FFT为291。与现有的实现方案相比，所提出的体系结构在可伸缩性和能效方面表现出更好的性能。

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