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首页> 外文期刊>Journal of materials science >Energy dissipation and constitutive modeling for a mechanistic description of pad scratching in chemical-mechanical planarization
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Energy dissipation and constitutive modeling for a mechanistic description of pad scratching in chemical-mechanical planarization

机译：能量耗散和本构模型，用于化学机械平面化中焊盘划痕的机械描述

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摘要

A thermomechanical model to describe the mechanisms of polishing pad scratching in chemical-mechanical planarization (CMP) has been formulated and investigated. CMP is a necessary process in integrated circuit (IC) fabrication to planarize wafers with nanoscale features after patterned layer deposition. Polishing pad asperities can produce microscale scratches on the wafer surface during CMP, reducing IC manufacturing yields. The constructed thermomechanical model accounts for stresses of the pad and wafer contact and also provides the means to track input energy dissipation during CMP. Tracking energy dissipation offers information about processes that may influence scratch production. This knowledge ultimately produces a greater physical understanding of CMP for the prevention of pad scratching. Polishing pad stress relaxation experiments demonstrate the importance of viscoelastic and plastic strain energy dissipation with its effects on the wafer stress field. Scratch producing ability of the polishing pad is found to decrease with use in CMP, with slurry soaking and increasing polishing time. Mechanical behavior of the polishing pad is demonstrated to differ when in compression and in tension. Compressibility of the pad material is shown to be significant in stress modeling through experimental measurement of polishing pad volume change. Differential scanning calorimetry of used polishing pad samples revealed energy dissipation into the polishing pad surface with increasing polishing time of CMP. Energy dissipation processes influence pad scratching in CMP. Analytical wafer stress field modeling unveils that the scratching ability of a polishing pad decreases when it is less stiff or has a smoother surface.
机译：建立并研究了一种热机械模型，用于描述化学机械平面化（CMP）中抛光垫刮擦的机理。 CMP是集成电路（IC）制造中在图案化层沉积后将具有纳米级特征的晶片平面化的必要工艺。 CMP期间，抛光垫粗糙会在晶片表面产生微小的划痕，从而降低IC的生产良率。所构建的热力学模型考虑了焊盘和晶圆接触的应力，并提供了在CMP期间跟踪输入能量耗散的方法。跟踪能耗会提供有关可能影响刮擦生产的过程的信息。这些知识最终将对CMP产生更深刻的物理理解，以防止焊盘刮擦。抛光垫应力松弛实验证明了粘弹性和塑性应变能消散的重要性及其对晶片应力场的影响。发现抛光垫的划痕产生能力随着在CMP中的使用而降低，随着浆料的浸泡和增加的抛光时间。已证明抛光垫的机械性能在压缩和拉伸时有所不同。通过对抛光垫体积变化的实验测量，表明垫材料的可压缩性在应力建模中具有重要意义。使用过的抛光垫样品的差示扫描量热法表明，随着CMP抛光时间的增加，能量会耗散到抛光垫表面。能量消耗过程会影响CMP中的焊盘划痕。分析性晶片应力场建模表明，抛光垫的硬度较小或表面较光滑时，其划伤能力会降低。

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  • 来源
    《Journal of materials science》 |2016年第2期|1745-1757|共13页
  • 作者

    David C. Ponte; D. M. L. Meyer;

  • 作者单位

    Mechanical Engineering, University of Rhode Island, Kingston, RI, USA;

    Mechanical Engineering, University of Rhode Island, Kingston, RI, USA;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
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  • 正文语种 eng
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