Wafer Extension For Cost-Effective front to Back Side Alignment

S. Brabender; K. Kolander; K. T. Kallis; H. L. Fiedler

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Wafer Extension For Cost-Effective front to Back Side Alignment

机译：晶圆扩展，实现了经济有效的前后对齐

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This work presents a cost-effective and simple possibility to outperform the potential of a standard single side mask aligner. The limited functionality is extended to the capability of back side alignment with minimal effort without additional knowledge and integration of new process technologies. The whole presented process flow performs without the necessity of additional equipment as infrared back side wafer alignment kits or additional etching processes or clamps and brackets. The result is a front to back side alignment process with satisfactory deviation.

机译：这项工作提供了一种经济有效且简单的方法，可以胜过标准的单面掩模对准器的潜力。有限的功能扩展到背面对齐的能力，而无需额外的知识和新工艺技术的集成，而花费最少的精力。所呈现的整个工艺流程无需使用诸如红外背面晶圆对准套件或其他蚀刻工艺或夹具和托架之类的附加设备即可执行。结果是具有令人满意的偏差的从正面到背面的对准过程。

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来源
《Journal of nano research》 |2014年第2014期|1-4|共4页
作者
S. Brabender; K. Kolander; K. T. Kallis; H. L. Fiedler;
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作者单位

Faculty of Electrical Engineering, TU Dortmund University,Emil-Figge-Str. 68, 44227 Dortmund, Germany;

Faculty of Electrical Engineering, TU Dortmund University,Emil-Figge-Str. 68, 44227 Dortmund, Germany;

Faculty of Electrical Engineering, TU Dortmund University,Emil-Figge-Str. 68, 44227 Dortmund, Germany;

Faculty of Electrical Engineering, TU Dortmund University,Emil-Figge-Str. 68, 44227 Dortmund, Germany;

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原文格式 PDF
正文语种 eng
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关键词
lithography; 3D integration; back side alignment; two-sided mask aligner;

机译：光刻3D整合;背面对齐;双面掩模对准器;

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1. Rigorous coupled wave analysis of front-end-of-line wafer alignment marks [J] . Swee Hock Yeo, Chin Boon Tan, Andrew Khoh Journal of Vacuum Science & Technology. B, Microelectronics and Nanometer Structures . 2005,第1期

机译：前端晶圆对准标记的严格耦合波分析
2. Silicon Alignment Pins: An Easy Way To Realize a Wafer-to-Wafer Alignment [J] . NASA Tech Briefs . 2013,第12期

机译：硅对准销：实现晶片对晶片对准的简便方法
3. Improved scanner exposure control to suppress process-related wafer-to-wafer deformation by an Improved wafer pre-alignment methodology [J] . Research Disclosure . 2018,第656期

机译：改进的扫描仪曝光控制，通过改进的晶片预对准方法来抑制与工艺相关的晶片间变形
4. New method of correlating product wafer yield to alignment performance and an optimized accounting method for product wafer alignment [C] . Hao Zhou, Rockwell Semiconductor Systems, Inc., Conference on metrology, inspection, and process control for microlithography . 1998

机译：将产品晶圆产量与对准性能相关联的新方法以及用于产品晶圆对准的优化核算方法
5. Cost-Effective Integrated Wireless Monitoring of Wafer Cleanliness Using SOI Technology. [D] . Pandit, Vedhas. 2010

机译：采用SOI技术的经济高效的晶圆清洁度集成无线监控。
6. Route to Cost-Effective Fabrication of Wafer-Scale Nanostructure through Self-Priming Nanoimprint [O] . Yue Su, Zhaoxin Geng, Weihao Fang, 2021

机译：通过自灌注纳米压印来实现晶片级纳米结构的经济高效制作的途径
7. Wafer Extension For Cost-Effective front to Back Side Alignment [O] . S. Brabendera, K. Kol, K. T. Kallis, 2015

机译：晶圆延伸，实现经济高效的前后对齐

Wafer Extension For Cost-Effective front to Back Side Alignment

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