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首页> 外文期刊>Journal of VLSI signal processing >POLYBiNN: Binary Inference Engine for Neural Networks using Decision Trees
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POLYBiNN: Binary Inference Engine for Neural Networks using Decision Trees

机译：POLYBiNN：使用决策树的神经网络二进制推理引擎

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Convolutional Neural Networks (CNNs) and Deep Neural Networks (DNNs) have gained significant popularity in several classification and regression applications. The massive computation and memory requirements of DNN and CNN architectures pose particular challenges for their FPGA implementation. Moreover, programming FPGAs requires hardware-specific knowledge that many machine-learning researchers do not possess. To make the power and versatility of FPGAs available to a wider deep learning user community and to improve DNN design efficiency, we introduce POLYBiNN, an efficient FPGA-based inference engine for DNNs and CNNs. POLYBiNN is composed of a stack of decision trees, which are binary classifiers in nature, and it utilizes AND-OR gates instead of multipliers and accumulators. POLYBiNN is a memory-free inference engine that drastically cuts hardware costs. We also propose a tool for the automatic generation of a low-level hardware description of the trained POLYBiNN for a given application. We evaluate POLYBiNN and the tool for several datasets that are normally solved using fully connected layers. On the MNIST dataset, when implemented in a ZYNQ-7000 ZC706 FPGA, the system achieves a throughput of up to 100 million image classifications per second with 90 ns latency and 97.26% accuracy. Moreover, POLYBiNN consumes 8x less power than the best previously published implementations, and it does not require any memory access. We also show how POLYBiNN can be used instead of the fully connected layers of a CNN and apply this approach to the CIFAR-10 dataset.
机译：卷积神经网络（CNN）和深层神经网络（DNN）在几种分类和回归应用程序中已获得广泛普及。 DNN和CNN架构对大量计算和内存的需求对其FPGA实施提出了特殊挑战。此外，对FPGA进行编程需要许多机器学习研究人员所不具备的特定于硬件的知识。为了使FPGA的功能强大和多功能性可用于更广泛的深度学习用户社区并提高DNN设计效率，我们引入了POLYBiNN，这是一种针对DNN和CNN的基于FPGA的高效推理引擎。 POLYBiNN由一堆决策树组成，决策树本质上是二进制分类器，它利用AND-OR门代替乘法器和累加器。 POLYBiNN是一种无内存推理引擎，可以大大降低硬件成本。我们还提出了一种工具，用于针对给定的应用程序自动生成经过培训的POLYBiNN的低级硬件描述。我们评估POLYBiNN和该工具的几个数据集，这些数据集通常使用完全连接的层来求解。在MNIST数据集上，当在ZYNQ-7000 ZC706 FPGA中实现时，该系统以90 ns的延迟和97.26％的精度实现每秒高达1亿个图像分类的吞吐量。此外，POLYBiNN的功耗比以前发布的最佳实施方案少8倍，并且不需要任何内存访问。我们还将展示如何使用POLYBiNN代替CNN的完全连接层，并将这种方法应用于CIFAR-10数据集。

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