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首页> 外文期刊>Journal of Spacecraft Technology >Indigenous Development of Intellectual Property Core for MIL-STD-1553B Remote Terminal
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Indigenous Development of Intellectual Property Core for MIL-STD-1553B Remote Terminal

机译：MIL-STD-1553B远程终端的知识产权核心的土着发展

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MIL-STD-1553, Digital Time Division Command/Response Multiplex Data Bus is widely being used for control and commanding purposes in various military, avionics and space applications. The standard defines mechanical, electrical and functional characteristics of the serial data bus. It categorises hardware elements into four types namely, 1) Bus Controller, 2) Remote Terminal, 3) Bus Monitor, 4) Transmission media. This paper discusses in detail an indigenously developed Intellectual Property core for MIL-STD-1553B Remote Terminal for which copyrights have been granted to ISRO in Dec 2015. 1553 technology is evolving from dedicated hardware chip to portable Intellectual Property cores. This considerably offers several advantages like smaller footprint, flexibility, lower cost, etc. Prime benefit of this IP Core is that it is technology independent which makes it possible to port it on any FPGA or customized ASIC device. Indigenously developed MIL-STD-1553 IP core design has been incorporated in On Board Controller ASICs developed by SAC. The IP core has also been incorporated as part of NAVIC receiver to be used in launch vehicles.
机译：MIL-STD-1553，数字时分指令/响应多路复用数据总线广泛用于各种军用，航空电子设备和空间应用中的控制和指挥目的。该标准定义了串行数据总线的机械，电气和功能特性。它将硬件元素分为四种类型，即1）总线控制器，2）远程终端，3）总线显示器，4）传输介质。本文详细讨论了用于MIL-STD-1553B远程终端的本质开发的知识产权核心，在2015年12月被授予ISRO .1553技术正在从专用硬件芯片到便携式知识产权核心的技术。这大大提供了较小的足迹，灵活性，较低的成本等多种优点。此IP核心的主要福利是它是技术独立的，这使得它可以将其移植到任何FPGA或定制ASIC设备上。本土发生开发的MIL-STD-1553 IP核心设计已被纳入由SAC开发的船上控制器ASIC。 IP核心也被纳入了用于在发动车辆中使用的纽波接收器的一部分。

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