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Implementation of the SHA-2 Hash Family Standard Using FPGAs

机译：使用FPGA实现SHA-2哈希系列标准

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摘要

The continued growth of both wired and wireless communications has triggered the revolution for the generation of new cryptographic algorithms. SHA-2 hash family is a new standard in the widely used hash functions category. An architecture and the VLSI implementation of this standard are proposed in this work. The proposed architecture supports a multi-mode operation in the sense that it performs all the three hash functions (256, 384 and 512) of the SHA-2 standard. The proposed system is compared with the implementation of each hash function in a separate FPGA device. Comparing with previous designs, the introduced system can work in higher operation frequency and needs less silicon area resources. The achieved performance in the term of throughput of the proposed system/architecture is much higher (in a range from 277 to 417%) than the other hardware implementations. The introduced architecture also performs much better than the implementations of the existing standard SHA-1, and also offers a higher security level strength. The proposed system could be used for the implementation of integrity units, and in many other sensitive cryptographic applications, such as, digital signatures, message authentication codes and random number generators.
机译：有线和无线通信的持续增长引发了新一代密码算法的革命。 SHA-2哈希家族是广泛使用的哈希函数类别中的新标准。在这项工作中提出了该标准的体系结构和VLSI实现。在执行SHA-2标准的所有三个哈希函数（256、384和512）的意义上，所提出的体系结构支持多模式操作。将提出的系统与单独的FPGA器件中每个哈希函数的实现进行了比较。与以前的设计相比，引入的系统可以在更高的工作频率下工作，并且需要更少的硅面积资源。在拟议的系统/体系结构的吞吐量方面实现的性能要比其他硬件实现方案高得多（在277％至417％之间）。引入的体系结构还比现有标准SHA-1的实现要好得多，并且还提供了更高的安全级别强度。所提出的系统可以用于实现完整性单元，并可以用于许多其他敏感的密码应用程序中，例如数字签名，消息验证码和随机数生成器。

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