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首页> 外文期刊>Journal of Vacuum Science & Technology. B, Microelectronics and Nanometer Structures >Fabrication of 22 nm half-pitch silicon lines by single-exposure self-aligned spatial-frequency doubling
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Fabrication of 22 nm half-pitch silicon lines by single-exposure self-aligned spatial-frequency doubling

机译:通过单曝光自对准空间倍频制造22 nm半间距硅线

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The relentless progression of semiconductor technology to smaller feature sizes will likely soon outstrip the theoretical linear system limits of today's optical lithography tools (a half-pitch of λ/4n or 34 nm with a 193 nm wavelength source and water immersion). We demonstrate a self-aligned process involving only a single lithographic exposure followed by spatial-frequency doubling that results a half-scaling of the original pattern and have achieved a 22 nm half-pitch pattern with 193 nm water immersion. A lithographic pitch of 89 nm was realized with a 193 nm ArF-excimer laser source and de-ionized-water immersion interferometric lithography. A self-aligned spatial-frequency doubling technique, taking advantage of the well-known anisotropic etching of silicon by KOH, was used to affect the frequency doubling. A protective layer (metal) was deposited parallel to the (110) direction of a (100) silicon wafer and the sample was immersed in an appropriate KOH solution, resulting in a series of 44.5 nm opening width V-grooves terminated in 57° (111) faces etched into the silicon through the mask openings. The metal mask was removed to expose the previously protected high-etch rate (100) surface of the sample for a second wet KOH etch. This results in a pattern at twice the original spatial frequency. A frequency-doubled pitch of 44.5 nm was achieved. An alternate, manufacturing friendly, processing scheme related to standard gate sidewall passivation is proposed.
机译:半导体技术无休止地发展为更小的特征尺寸,可能很快就会超过当今光学光刻工具的理论线性系统极限(λ/ 4n的半节距或193 nm波长源和水浸的34 nm)。我们展示了一种仅包含单次光刻曝光,然后进行空间-频率加倍的自对准过程,该过程导致原始图案的一半缩放,并通过193 nm的水浸实现了22 nm的半间距图案。使用193 nm ArF准分子激光源和去离子水浸没干涉光刻技术,可实现89 nm的光刻间距。利用自对准的空分频技术,利用众所周知的KOH对硅进行各向异性刻蚀,来影响倍频。平行于(100)硅片的(110)方向沉积保护层(金属),并将样品浸入适当的KOH溶液中,从而形成一系列44.5 nm开口宽度的V型槽,终止于57°( 111)的面通过掩模开口蚀刻到硅中。去除金属掩模以暴露出先前保护的样品的高蚀刻速率(100)表面,以进行第二次湿KOH蚀刻。这导致图案是原始空间频率的两倍。实现了44.5 nm的倍频间距。提出了与标准栅极侧壁钝化有关的另一种制造友好的处理方案。

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