Effect of Si interlayer thickness and post-metallization annealing on Ge MOS capacitor on Ge-on-Si substrate

Ook Sang Yoo; Jungwoo Oh; Chang Yong Kang; Byoung Hun Lee; In Shik Han; Won-Ho Choi; Hyuk-Min Kwon; Min-Ki Na; Prashant Majhi; Hsing-Huang Tseng; Raj Jammy; Jin Suk Wang; Hi-Deok Lee

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Effect of Si interlayer thickness and post-metallization annealing on Ge MOS capacitor on Ge-on-Si substrate

机译：Si层间厚度和金属化后退火对Ge-on-Si衬底上Ge MOS电容器的影响

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We demonstrated the effect of post-metallization annealing and Si interlayer thickness on Ge MOS capacitor on Ge-on-Si substrate with HfO_2/TaN. Ge outdiffusion and oxygen interdiffusion were completely suppressed by thick Si interfacial layer. As a result, formation of insufficient low-K Ge oxides was effectively inhibited. It is confirmed that gate current of Si passivated Ge MOS was decreased by Si IL and decrease of gate current, J_g is saturated after Si IL of 2 nm. It was also observed that when Si IL is thick enough to restrict Ge outdiffusion, increase of J_g is not due to the temperature-induced Ge outdiffusion but due to the partial crystallization of HfO_2 at higher annealing temperature.

机译：我们证明了用HfO_2 / TaN对Ge-on-Si衬底上的Ge MOS电容器进行金属化后退火和Si中间层厚度的影响。厚的Si界面层完全抑制了Ge的扩散和氧的扩散。结果，有效地抑制了不足的低K Ge氧化物的形成。可以确定，Si钝化的Ge MOS的栅极电流被Si IL降低，栅极电流的降低，在Si IL为2 nm之后，J_g达到饱和。还观察到，当Si IL足够厚以限制Ge向外扩散时，J_g的增加不是由于温度引起的Ge向外扩散，而是由于HfO_2在较高的退火温度下部分结晶。

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来源
《Materials Science and Engineering》 |2008年第2008期|p.102-105|共4页
作者
Ook Sang Yoo; Jungwoo Oh; Chang Yong Kang; Byoung Hun Lee; In Shik Han; Won-Ho Choi; Hyuk-Min Kwon; Min-Ki Na; Prashant Majhi; Hsing-Huang Tseng; Raj Jammy; Jin Suk Wang; Hi-Deok Lee;
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SEMATECH, 2706 Montopolis Dr., Austin, TX 78741, USA Department of Electronics Engineering, Chungnam National University, 220 ding-dong, Yuseong-Gu, Daejeon 305-764, Republic of Korea;

SEMATECH, 2706 Montopolis Dr., Austin, TX 78741, USA;

SEMATECH, 2706 Montopolis Dr., Austin, TX 78741, USA;

SEMATECH, 2706 Montopolis Dr., Austin, TX 78741, USA;

Department of Electronics Engineering, Chungnam National University, 220 ding-dong, Yuseong-Gu, Daejeon 305-764, Republic of Korea;

SEMATECH, 2706 Montopolis Dr., Austin, TX 78741, USA Department of Electronics Engineering, Chungnam National University, 220 ding-dong, Yuseong-Gu, Daejeon 305-764, Republic of Korea;

Department of Electronics Engineering, Chungnam National University, 220 ding-dong, Yuseong-Gu, Daejeon 305-764, Republic of Korea;

Department of Electronics Engineering, Chungnam National University, 220 ding-dong, Yuseong-Gu, Daejeon 305-764, Republic of Korea;

SEMATECH, 2706 Montopolis Dr., Austin, TX 78741, USA;

SEMATECH, 2706 Montopolis Dr., Austin, TX 78741, USA;

SEMATECH, 2706 Montopolis Dr., Austin, TX 78741, USA;

Department of Electronics Engineering, Chungnam National University, 220 ding-dong, Yuseong-Gu, Daejeon 305-764, Republic of Korea;

Department of Electronics Engineering, Chungnam National University, 220 ding-dong, Yuseong-Gu, Daejeon 305-764, Republic of Korea;

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正文语种 eng
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关键词
Ge; Si capping; surface passivation; post-metallization annealing;

机译：葛;硅盖;表面钝化;后金属化退火;

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Effect of Si interlayer thickness and post-metallization annealing on Ge MOS capacitor on Ge-on-Si substrate

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