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Embedded FPGA Design for Optimal Pixel Adjustment Process of Image Steganography

机译：用于图像隐写术的最佳像素调整过程的嵌入式FPGA设计

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摘要

We propose a prototype of field programmable gate array (FPGA) implementation for optimal pixel adjustment process (OPAP) algorithm of image steganography. In the proposed scheme, the cover image and the secret message are transmitted from a personal computer (PC) to an FPGA board using RS232 interface for hardware processing. We firstly embed k-bit secret message into each pixel of the cover image by the last-significant-bit (LSB) substitution method, followed by executing associated OPAP calculations to construct a stego pixel. After all pixels of the cover image have been embedded, a stego image is created and transmitted from FPGA back to the PC and stored in the PC. Moreover, we have extended the basic pixel-wise structure to a parallel structure which can fully use the hardware devices to speed up the embedding process and embed several bits of secret message at the same time. Through parallel mechanism of the hardware based design, the data hiding process can be completed in few clock cycles to produce steganography outcome. Experimental results show the effectiveness and correctness of the proposed scheme.
机译：我们提出了一种现场可编程门阵列（FPGA）实现的原型，以实现图像隐写术的最佳像素调整过程（OPAP）算法。在提出的方案中，封面图像和秘密消息使用RS232接口从个人计算机（PC）传输到FPGA板，以进行硬件处理。我们首先通过最后有效位（LSB）替换方法将k位秘密消息嵌入到封面图像的每个像素中，然后执行关联的OPAP计算以构造隐身像素。嵌入封面图像的所有像素后，将创建一个隐藏图像并将其从FPGA传输回PC并存储在PC中。此外，我们已经将基本的逐像素结构扩展为并行结构，可以充分利用硬件设备来加快嵌入过程，并同时嵌入几位秘密消息。通过基于硬件的并行设计机制，可以在几个时钟周期内完成数据隐藏过程，从而产生隐写结果。实验结果表明了该方案的有效性和正确性。

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