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首页> 外文期刊>Microelectronic Engineering >Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors
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Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

机译：在三栅极SOI无结纳米线晶体管中模拟与接口陷阱相关的低频噪声

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摘要

The aim of this work is to propose a semi-analytical model for the low frequency noise caused by interface traps in Triple-Gate Junctionless Nanowire Transistors. The proposed model is based on a drain current model, which includes short channel effects influence. The surface potential and the occupied trap density equations are solved self consistently to obtain the traps influence in the static drain current, which is used to determine the trap related noise. In this work, the low frequency noise of traps in discrete levels is analyzed. The model has been validated with 3D simulations considering different devices characteristics, biases and trap levels. Experimental results have also been used to demonstrate the model suitability.
机译：这项工作的目的是为三栅极无结纳米线晶体管中的界面陷阱所引起的低频噪声提出一个半分析模型。所提出的模型基于漏极电流模型，该模型包括短沟道效应的影响。表面电势和占据的陷阱势方程可以自洽地求解，从而获得陷阱对静态漏极电流的影响，从而确定与陷阱有关的噪声。在这项工作中，分析了离散级陷阱的低频噪声。该模型已通过3D仿真进行了验证，其中考虑了不同的器件特性，偏置和陷阱水平。实验结果也已用于证明模型的适用性。

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