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Study of the effect of tunneling through the traps inside the insulator on small-signal admittance of the MOS structure

机译:研究通过绝缘子内部陷阱的隧道对MOS结构小信号导纳的影响

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摘要

The effect of tunneling through traps located inside the insulator layer on the small-signal admittance parameters of the MOS tunnel diode is investigated by means of the theoretical model. An influence of geometric and energy positions of the traps is studied. The model and considerations are confirmed by a comparison with measurement data of an experimental Al-SiO_2-Si structure.
机译:通过理论模型研究了通过位于绝缘体层内部的陷阱进行隧穿对MOS隧道二极管的小信号导纳参数的影响。研究了陷阱的几何和能量位置的影响。通过与实验Al-SiO_2-Si结构的测量数据进行比较,确定了模型和考虑因素。

著录项

  • 来源
    《Microelectronic Engineering》 |2013年第9期|1-4|共4页
  • 作者单位

    Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, Warsaw, Poland;

    Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, Warsaw, Poland;

    Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, Warsaw, Poland;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Insulator traps; Tunneling; Admittance model; MOS tunnel diode;

    机译:绝缘子陷阱;隧道准入模型MOS隧道二极管;

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