Some issues in advanced CMOS gate stack performance and reliability

著录项

• 来源
  《Microelectronic Engineering》 |2011年第12期|p.3377-3384|共8页
• 作者

  Ming-Fu Li; X.P. Wang; C. Shen; J.J. Yang; J.D. Chen; H.Y. Yu; Chunxiang Zhu; Darning Huang;

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• 作者单位

  State Key Lab ASIC & Syst, Dept. Microelectronics, Fudan University, Shanghai 201203, China,SNDL, ECE Dept., National University of Singapore, Singapore 117576, Singapore;

  SNDL, ECE Dept., National University of Singapore, Singapore 117576, Singapore;

  SNDL, ECE Dept., National University of Singapore, Singapore 117576, Singapore;

  SNDL, ECE Dept., National University of Singapore, Singapore 117576, Singapore;

  SNDL, ECE Dept., National University of Singapore, Singapore 117576, Singapore;

  School ofEEE, Nanyang Technological University, Singapore 639798, Singapore;

  SNDL, ECE Dept., National University of Singapore, Singapore 117576, Singapore;

  State Key Lab ASIC & Syst, Dept. Microelectronics, Fudan University, Shanghai 201203, China;

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• 原文格式 PDF
• 正文语种 eng
• 中图分类
• 关键词

  CMOS; gate stack; reliability;

  机译：CMOS;门叠可靠性;