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Bit-width-aware constant-delay run-time Accuracy Programmable Adder for error-resilient applications

机译:可识别位宽的恒定延迟运行时精度可编程加法器,用于具有弹性的应用

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Error-resilient applications such as image, audio and video processing adopt the concept of approximate computing to decorate delay, power and area metrics at the cost of accuracy. Approximate computing relaxes the exact equivalence between the design specifications and the design implementation to achieve Speed-Power-Accuracy-Area (SPAA) trade-off. In this paper, we propose a bit-width-aware constant-delay run-time Accuracy Programmable Adder (APA) in which the probability of input combinations exhibiting accurate results is programmable and adaptively controlled by the Number of Iterations (Nols). Simulation results based on the PTM 32 nm CMOS technology suggest that the proposed approach attains tremendous improvements in delay, power and area metrics with a trivial degradation in the output quality. The proposed APA shows 3.4 x improvement in performance and 41.5% reduction in area over the best known accuracy configurable adder. Even with 100% accuracy, a 32-bit APA improves delay, power and area by 33.92%, 23.04% and 17.44%, respectively, over Ripple Carry Adder (RCA). We also demonstrate an APA embedded error-resilient JPEG encoder architecture in order to inspect the efficacy of the proposed approach in real-time Digital Signal Processing (DSP) applications. (C) 2016 Elsevier Ltd. All rights reserved.
机译:诸如图像,音频和视频处理之类的具有容错能力的应用程序采用近似计算的概念,以准确性为代价来装饰延迟,功率和面积指标。近似计算可放宽设计规范与设计实现之间的精确对等,以实现速度-功率-精度-面积(SPAA)的权衡。在本文中,我们提出了一种位宽感知的恒定延迟运行时精度可编程加法器(APA),其中输入组合呈现准确结果的概率是可编程的,并由迭代次数(Nols)自适应控制。基于PTM 32 nm CMOS技术的仿真结果表明,所提出的方法在延迟,功率和面积指标方面取得了巨大的改进,而输出质量却微不足道。与最著名的精度可配置加法器相比,建议的APA在性能上提高了3.4倍,在面积上减少了41.5%。即使具有100%的精度,与Ripple Carry Adder(RCA)相比,32位APA仍可将延迟,功率和面积分别提高33.92%,23.04%和17.44%。我们还演示了APA嵌入式防错JPEG编码器体系结构,以检查所提出方法在实时数字信号处理(DSP)应用中的功效。 (C)2016 Elsevier Ltd.保留所有权利。

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