A 12 bit 250 MS/s 28 mW+70 dB SFDR non-50% RZ DAC in 0.11 mu m CMOS using controllable RZ window for wireless SoC integration

Kim Seonggeon; Kang Jaehyun; Lee Minjae

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A 12 bit 250 MS/s 28 mW+70 dB SFDR non-50% RZ DAC in 0.11 mu m CMOS using controllable RZ window for wireless SoC integration

机译：一个12位250 MS / s 28 mW + 70 dB SFDR非50％RZ DAC，采用0.11μmCMOS，使用可控制的RZ窗口进行无线SoC集成

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摘要

A 12-bit current-steering digital-to-analog converter (DAC) in 0.11 mu m CMOS technology is presented for one DAC with a flexible swing and common-mode voltage for both an IQ baseband wireless transmitter (TX) and an envelope tracking (ET) power amplifier that require low power consumption. :The conventional half clock period return-to-zero (RZ) effectively eliminates the code-dependent transient but results in amplitude loss and larger DAC images. The proposed RZ flip-flop generates a controllable RZ signal with a clock duty cycle that is less than 50%, which mitigates such a signal power loss and relaxes the image filtering requirement. In addition, this DAC can easily switch between non-return-to-zero (NRZ) mode and RZ mode to serve various applications. The implemented DAC is character-ized at the sample frequency of 250 MHz and it achieves a spurious-free dynamic range (SFDR) greater than 70 dB up to the Nyquist frequency. The core area of the DAC is 0.117 mm(2) and it dissipates about 28 mW under a 2.5 V supply. (C) 2016 Elsevier Ltd. All rights reserved.

机译：提出了一种采用0.11μmCMOS技术的12位电流控制数模转换器（DAC），该器件用于IQ基带无线发射机（TX）和包络跟踪的一种具有灵活摆幅和共模电压的DAC （ET）要求低功耗的功率放大器。：传统的半时钟周期归零（RZ）有效消除了与代码有关的瞬变，但会导致幅度损失和较大的DAC图像。所提出的RZ触发器产生具有小于50％的时钟占空比的可控RZ信号，这减轻了这种信号功率损耗并放松了图像滤波要求。此外，该DAC可以轻松地在不归零（NRZ）模式和RZ模式之间切换，以服务各种应用。实施的DAC在250 MHz的采样频率下进行特性分析，在奈奎斯特频率之前，其无杂散动态范围（SFDR）大于70 dB。 DAC的核心面积为0.117 mm（2），在2.5 V电源下的功耗约为28 mW。（C）2016 Elsevier Ltd.保留所有权利。

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来源
《Microelectronics journal》 |2016年第10期|46-56|共11页
作者
Kim Seonggeon; Kang Jaehyun; Lee Minjae;
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作者单位

Gwangju Inst Sci & Technol, Sch Elect Engn & Comp Sci, Bukgu, South Korea;

Silicon Works, Business Div, Driver IC Team, Daejeon, South Korea;

Gwangju Inst Sci & Technol, Sch Elect Engn & Comp Sci, Bukgu, South Korea;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类
关键词
Digital-to-analog converter (DAC); Dynamic-element matching (DEM); Return-to-zero (RZ); Spurious-free dynamic range (SFDR); Signal-to-noise ratio (SNR); Noise spectral density (NSD);

机译：数模转换器（DAC）;动态元素匹配（DEM）;归零（RZ）;无杂散动态范围（SFDR）;信噪比（SNR）;噪声频谱密度（ NSD）;

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1. A 12-bit 250 MS/s pipeline ADC with 78 dB SFDR in 0.13-μm CMOS [J] . Sun Jie, Wu Jianhui International journal of electronics . 2018,第7a9期

机译：具有0.13μmCMOS的78位SFDR的12位250 MS / s流水线ADC
2. A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with over 80-dB SFDR [J] . Hui Pan, Segami M. IEEE Journal of Solid-State Circuits . 2000,第12期

机译：具有0.6- / splμ/ m CMOS的3.3V 12-b 50-MS / s A / D转换器，具有超过80dB的SFDR
3. A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz [J] . Radulov Georgi I., Quinn Patrick J., van Roermund Arthur H. M. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2015,第9期

机译：具有DfT时钟且存储器达到SFDR> 50 dB且高达1 GHz的28nm CMOS 7-GS / s 6位DAC
4. A 12 bit 250 MS/s 28 mW +70 dB SFDR DAC in 0.11 μm CMOS using controllable RZ window for wireless SoC integration [C] . Seonggeon Kim, Jaehyun Kang, Minjae Lee IEEE Asian Solid State Circuits Conference . 2014

机译：使用可控制的RZ窗口，0.11μmCMOS的12位250 MS / s 28 mW +70 dB SFDR DAC，用于无线SoC集成

A 12 bit 250 MS/s 28 mW+70 dB SFDR non-50% RZ DAC in 0.11 mu m CMOS using controllable RZ window for wireless SoC integration

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