A delay-locked loop with self-calibration circuit for reducing phase error

Shao-ku Kao

首页> 外文期刊>Microelectronics journal >A delay-locked loop with self-calibration circuit for reducing phase error

【24h】

A delay-locked loop with self-calibration circuit for reducing phase error

机译：具有自校准电路的延迟锁定环路，可减少相位误差

获取原文

获取原文并翻译 | 示例

掌桥外文数据库（机构版） >>

开具论文收录证明 >>

文献代查 >>

页面导航

摘要
著录项
相似文献
相关主题

摘要

A delay-locked loop with self-calibration circuit for reducing phase error is presented. In this DLL, the current mismatch adjusting circuit is proposed in order to reduce the static phase error. To reduce the static phase error the circuit eliminates the mismatch of up/down currents in the charge pump (CP). The current mismatch adjusting circuit is implemented with phase expanded circuit to amplifier the static phase error. To solve the false locking problem, a new phase detector is proposed. The proposed circuit has been fabricated in a 0.18 μm CMOS process. The measured static phase errors are without and with calibration circuit are 29 ps and 3.89 ps at 1.2 GHz, respectively.

机译：提出了一种具有自校准电路的延迟锁定环路，用于减少相位误差。在该DLL中，提出了电流失配调节电路，以减小静态相位误差。为了减少静态相位误差，该电路消除了电荷泵（CP）中上/下电流的不匹配。电流失配调节电路通过相扩展电路实现，以放大静态相位误差。为了解决误锁定问题，提出了一种新型的鉴相器。所提出的电路已经以0.18μmCMOS工艺制造。在没有校准电路和有校准电路的情况下，在1.2 GHz时测得的静态相位误差分别为29 ps和3.89 ps。

著录项

来源
《Microelectronics journal》 |2013年第8期|663-669|共7页
作者
Shao-ku Kao;
展开▼
作者单位

Department of Electrical Engineering and Green Technology Research Center, Chang Gung University, Tao-Yuan, Taiwan, ROC;

展开▼
收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类
关键词
Current mismatch; Charge pump (CP); Static phase error; Delay-locked loop (DLL);

机译：当前不匹配;补油泵（CP）;静态相位误差;延迟锁定循环（DLL）;

相似文献

外文文献
中文文献
专利

1. A phase-locked loop with background self-calibration for phase error reduction [J] . Shao-Ku Kao, Po-Tsun Wu, Yu-Zhang Lee International Journal of Electronics Letters . 2015,第2期

机译：具有背景自校准功能的锁相环，可减少相位误差
2. A self-calibrated delay-locked loop with low static phase error [J] . Kao Shao-Ku, Cheng Hsiang-Chi, Lin Jian-Da International journal of circuit theory and applications . 2016,第4期

机译：具有低静态相位误差的自校准延迟锁定环路
3. 100-phase, dual-loop delay-locked loop for impulse radio ultra-wideband coherent receiver synchronisation [J] . Xia L., Chen H., Huang Y., Circuits, Devices & Systems, IET . 2011,第6期

机译：100相双回路延迟锁定回路，用于脉冲无线电超宽带相干接收机同步
4. A non-linearity self-calibration technique for delay-locked loop delay-lines [C] . Baronti F., Fanucci L., Lunardini D., Instrumentation and Measurement Technology Conference, 2002. IMTC/2002. Proceedings of the 19th IEEE . 2002

机译：延迟锁定回路延迟线的非线性自校准技术
5. Testing embedded phase-locked loops and delay-locked loops. [D] . Egan, Thomas Vincent. 2005

机译：测试嵌入式锁相环和延迟锁环。
6. Wideband Self-Calibration Method of Inductive CTs and Verification of Determined Values of Current and Phase Errors at Harmonics for Transformation of Distorted Current [O] . Ernest Stano, Michal Kaczmarek 2020

机译：感应CT的宽带自校准方法以及谐波电流转换时谐波的电流和相位误差确定值的验证
7. A Comprehensive Phase-Transfer Model for Delay-Locked Loops [O] . James R. Burnham, Gu-yeon Wei, Chih-kong Ken Yang, 2008

机译：延迟锁定环的综合相转移模型

A delay-locked loop with self-calibration circuit for reducing phase error

摘要

著录项

相似文献

相关主题

期刊订阅