...
首页> 外文期刊>Microelectronics journal >Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect
【24h】

Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect

机译:时空编码可提高片上互连的速度和噪声容限

获取原文
获取原文并翻译 | 示例
           

摘要

This paper introduces a new coding scheme that simultaneously tackles different design issues of interconnections such as noise, crosstalk and power consumption. The scheme is based on temporal skewing between data words on even and odd lines of an interconnection link, and its hardware implementation is simple and area-efficient. The proposed scheme permits to double the bandwidth of the interconnect while improving its noise tolerance. This is achieved through the simultaneous use of two error detecting techniques: temporal redundancy and parity. Improved noise tolerance property provided by our design enables to decrease the power supply voltage and hence to reduce power consumption of the interconnect.
机译:本文介绍了一种新的编码方案,该方案可同时解决互连的不同设计问题,例如噪声,串扰和功耗。该方案基于互连链路的偶数和奇数行上的数据字之间的时间偏移,并且其硬件实现简单而高效。所提出的方案允许将互连的带宽加倍,同时提高其噪声容限。这是通过同时使用两种错误检测技术来实现的:时间冗余和奇偶校验。我们的设计提供了改进的噪声容忍特性,从而可以降低电源电压,从而降低互连的功耗。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号