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Soft error modeling and remediation techniques in ASIC designs

机译:ASIC设计中的软错误建模和补救技术

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Soft errors due to cosmic radiations are the main reliability threat during lifetime operation of digital systems. Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system in order to balance reliability, performance, and cost of the system. Previous techniques for SER estimation are mainly based on fault injection and random simulations. In this paper, we present an analytical SER modeling technique for ASIC designs that can significantly reduce SER estimation time while achieving very high accuracy. This technique can be used for both combinational and sequential circuits. We also present an approach to obtain uncertainty bounds on estimated error propagation probability (EPP) values used in our SER modeling framework. Comparison of this method with the Monte-Carlo fault injection and simulation approach confirms the accuracy and speed-up of the presented technique for both the computed EPP values and uncertainty bounds. Based on our SER estimation framework, we also present efficient soft error hardening techniques based on selective gate resizing to maximize soft error suppression for the entire logic-level design while minimizing area and delay penalties. Experimental results confirm that these techniques are able to significantly reduce soft error rate with modest area and delay overhead.
机译:宇宙辐射引起的软错误是数字系统使用寿命期间的主要可靠性威胁。快速准确地估计软错误率(SER)对于获得数字系统的可靠性参数至关重要,以平衡系统的可靠性,性能和成本。先前的SER估计技术主要基于故障注入和随机仿真。在本文中,我们提出了一种用于ASIC设计的分析性SER建模技术,该技术可以显着减少SER估计时间,同时实现很高的精度。该技术可用于组合电路和顺序电路。我们还提出了一种方法,用于获取在我们的SER建模框架中使用的估计错误传播概率(EPP)值的不确定性范围。该方法与蒙特卡洛故障注入和仿真方法的比较证实了所计算技术的EPP值和不确定性边界的准确性和提速。基于我们的SER估计框架,我们还提出了基于选择性门调整大小的高效软错误强化技术,可在整个逻辑级设计中最大程度地抑制软错误,同时将面积和延迟损失降至最低。实验结果证实,这些技术能够以适度的面积和延迟开销显着降低软错误率。

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