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首页> 外文期刊>Microelectronics journal >Low power and high speed multiplier design with row bypassing and parallel architecture
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Low power and high speed multiplier design with row bypassing and parallel architecture

机译：具有行旁路和并行架构的低功耗和高速乘法器设计

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This paper presents a low power and high speed row bypassing multiplier. The primary power reductions are obtained by tuning off MOS components through multiplexers when the operands of multiplier are zero. Analysis of the conventional DSP applications shows that the average of zero input of operand in multiplier is 73.8 percent. Therefore, significant power consumption can be reduced by the proposed bypassing multiplier. The proposed multiplier adopts ripple-carry adder with fewer additional hardware components. In addition, the proposed bypassing architecture can enhance operating speed by the additional parallel architecture to shorten the delay time of the proposed multiplier. Both unsigned and signed operands of multiplier are developed. Post-layout simulations are performed with standard TSMC 0.18 urn CMOS technology and 1.8 V supply voltage by Cadence Spectre simulation tools. Simulation results show that the proposed design can reduce power consumption and operating speed compared to those of counterparts. For a 16 × 16 multiplier, the proposed design achieves 17 and 36 percent reduction in power consumption and delay, respectively, at the cost of 20 percent increase of chip area in comparison with those of conventional array multipliers. In addition, the proposed design achieves averages of 11 and 38 percent reduction in power consumption and delay with 46 percent less chip area in comparison with those counterparts for both unsigned and signed multipliers. The proposed design is suitable for low power and high speed arithmetic applications.
机译：本文提出了一种低功耗，高速行旁路乘法器。通过在乘法器的操作数为零时通过多路复用器关闭MOS组件来获得初级功耗降低。对常规DSP应用的分析表明，乘法器中操作数零输入的平均值为73.8％。因此，通过提出的旁路乘法器可以减少大量功耗。建议的乘法器采用带有少量硬件组件的纹波进位加法器。另外，所提出的旁路架构可以通过附加的并行架构来提高操作速度，从而缩短所提出的乘法器的延迟时间。乘数的无符号和有符号操作数均被开发。布局后的仿真是通过Cadence Spectre仿真工具使用标准的TSMC 0.18 umn CMOS技术和1.8 V电源电压进行的。仿真结果表明，与同类产品相比，该设计可以降低功耗和运行速度。对于16×16乘法器，与常规阵列乘法器相比，拟议的设计分别实现了17％和36％的功耗和延迟降低，而芯片面积却增加了20％。此外，与无符号和有符号乘法器的同类产品相比，拟议的设计在功耗和延迟方面平均降低了11％和38％，芯片面积减少了46％。所提出的设计适用于低功耗和高速算术应用。

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