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Yield enhancement techniques for 3-dimensional random access memories

机译：3维随机存取存储器的良率提高技术

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摘要

As the advances of process technology keep growing, three-dimensional (3D) integration with through silicon vias is a new alternative solution to extend Moore's law especially for random access memories (RAMs). In general, the reliability and fabrication yield of the traditional 2D memories can be improved by the incorporation of some form of redundancy. However, for 3D integration, the scenarios for the repair process are totally different. The redundancy exclusively added in a memory tier can also be reused to repair defects in the other memory tier after the bonding process. That is, the concept of inter-tier redundancy can be exploited to further increase the yield of 3D memories. Die-to-die and die-to-wafer bonding can be adopted. In this paper, we propose an efficient die-stacking flow and the corresponding built-in self-repair architectures for yield enhancement of 3D memories. The matching problem for die stacking can be converted into a bipartite graph maximal matching problem and the traditional algorithm can be used to solve this problem. Experimental results show that the proposed stacking flow, algorithm, and the corresponding BISR (built-in self-repair) architecture can improve fabrication yield significantly.
机译：随着制程技术的进步不断发展，通过硅通孔的三维（3D）集成是一种扩展替代摩尔定律的新的替代解决方案，特别是对于随机存取存储器（RAM）。通常，可以通过合并某种形式的冗余来提高传统2D存储器的可靠性和制造良率。但是，对于3D集成，修复过程的方案完全不同。在绑定过程之后，专门添加在存储层中的冗余也可以重新用于修复其他存储层中的缺陷。即，可以利用层间冗余的概念来进一步提高3D存储器的产量。可以采用管芯对管芯和管芯对晶片的键合。在本文中，我们提出了一种有效的裸片堆叠流程以及相应的内置自修复架构，以提高3D存储器的良率。可以将芯片堆叠的匹配问题转换为二部图最大匹配问题，并且可以使用传统算法来解决该问题。实验结果表明，所提出的堆叠流程，算法以及相应的BISR（内置自修复）架构可以显着提高制造良率。

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  • 来源
    《Microelectronics reliability》 |2012年第6期|p.1065-1070|共6页
  • 作者

    Shyue-Kung Lu; Tin-Wei Chang; Han-Yu Hsu;

  • 作者单位

    Dept. of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan;

    Dept. of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan;

    Dept. of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
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