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Implementation of a secure TLS coprocessor on an FPGA

机译：在FPGA上实现安全的TLS协处理器

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In this paper we present a secure implementation architecture of a coprocessor for the TLSv1.2 protocol, on an FPGA. Techniques were used that increase the resistance of the design to side channel attacks, and also protect the private key data from software based attacks. The processor was implemented with a secure true random number generator which incorporates failure detection and thorough post-processing of the random bitstream. The design also includes hardware for signature generation and verification; based on elliptic curve algorithms. The algorithms used for performing the elliptic curve arithmetic were chosen to provide resistance against SPA and DPA attacks. Implementations of the AES and SHA256 algorithms are also included in order to provide full hardware acceleration for a specific suite of the TLSv1.2 protocol. The design is analysed for area and speed on a Virtex 5 FPGA. (C) 2015 Elsevier B.V. All rights reserved.
机译：在本文中，我们介绍了在FPGA上针对TLSv1.2协议的协处理器的安全实现架构。所使用的技术可以增加设计对旁通道攻击的抵抗力，还可以保护私钥数据免受基于软件的攻击。该处理器由安全的真实随机数生成器实现，该生成器结合了故障检测和随机比特流的彻底后处理功能。该设计还包括用于签名生成和验证的硬件；基于椭圆曲线算法。选择用于执行椭圆曲线算术的算法以提供对SPA和DPA攻击的抵抗力。还包括AES和SHA256算法的实现，以便为特定的TLSv1.2协议套件提供完整的硬件加速。在Virtex 5 FPGA上分析了设计的面积和速度。 （C）2015 Elsevier B.V.保留所有权利。

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