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Real-time simulation of dynamic vehicle models using a high-performance reconfigurable platform

机译：使用高性能可重构平台实时仿真动态车辆模型

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With the increase in the complexity of models and lack of flexibility offered by the analog computers, coupled with the advancements in digital hardware, the simulation industry has subsequently moved to digital computers and increased usage of programming languages such as C, C++, and MATLAB. However, the reduced time-step required to simulate complex and fast systems imposes a tighter constraint on the time within which the computations have to be performed. The sequential execution of these computations fails to cope with the real-time constraints which further restrict the usefulness of Real-Time Simulation (RTS) in a Virtual Reality (VR) environment. In this paper, we present a methodology for the design and implementation of RTS algorithms, based on the use of Field-Programmable Gate Array (FPGA) technology. We apply our methodology to an 8th order steering valve subsystem of a vehicle with relatively low response time requirements and use the FPGA technology to improve the response time of this model. Our methodology utilizes traditional hardware/software co-design approaches to generate a heterogeneous architecture for an FPGA-based simulator by porting the computationally complex regions to hardware. The hardware design was optimized such that it efficiently utilizes the parallel nature of FPGAs and pipelines the independent operations. Further enhancement was made by building a hardware component library of custom accelerators for common non-linear functions. The library also stores the information about resource utilization, cycle count, and the relative error with different bit-width combinations for these components, which is further used to evaluate different partitioning approaches. In this paper, we illustrate the partitioning of a hardware-based simulator design across dual FPGAs, initiate RTS using a system input from a Hardware-in-the-Loop (Hit.) framework, and use these simulation results from our FPGA-based platform to perform response analysis. The total simulation time, which includes the time required to receive the system input over a socket (without HIL), software initialization, hardware computation, and transfer of simulation results back over a socket, shows a speedup of 2 x as compared to a similar setup with no hardware acceleration. The correctness of the simulation output from the hardware has also been validated with the simulated results from the software-only design. (C) 2015 Elsevier B.V. All rights reserved.
机译：随着模型复杂性的增加和模拟计算机所缺乏的灵活性，再加上数字硬件的进步，仿真行业随后转向数字计算机，并增加了诸如C，C ++和MATLAB之类的编程语言的使用。但是，减少模拟复杂快速系统所需的时间步长，在必须执行计算的时间上施加了更严格的约束。这些计算的顺序执行无法应付实时约束，而实时约束进一步限制了虚拟现实（VR）环境中实时仿真（RTS）的实用性。在本文中，我们基于现场可编程门阵列（FPGA）技术的使用，提出了一种设计和实现RTS算法的方法。我们将我们的方法应用于响应时间要求相对较低的车辆的8阶转向阀子系统，并使用FPGA技术来改善该模型的响应时间。我们的方法通过将计算复杂的区域移植到硬件上，利用传统的硬件/软件协同设计方法为基于FPGA的模拟器生成异构架构。对硬件设计进行了优化，以使其有效利用了FPGA的并行特性，并流水线进行了独立的操作。通过构建用于常见非线性功能的自定义加速器的硬件组件库，进一步增强了性能。该库还存储有关这些组件的资源利用率，周期数以及具有不同位宽组合的相对误差的信息，这些信息还用于评估不同的分区方法。在本文中，我们说明了跨双FPGA的基于硬件的仿真器设计的划分，使用来自硬件在环（Hit。）框架的系统输入来启动RTS，并使用基于FPGA的仿真结果平台进行响应分析。总仿真时间（包括通过套接字接收系统输入（不使用HIL），软件初始化，硬件计算以及通过套接字传回仿真结果所需的时间）显示，与类似情况相比，速度提高了2倍没有硬件加速的设置。硬件仿真输出的正确性也已通过纯软件设计的仿真结果进行了验证。 （C）2015 Elsevier B.V.保留所有权利。

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