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Design and benchmarking of an ASIC with five SHA-3 finalist candidates

机译：具有5位SHA-3入围候选人的ASIC的设计和基准测试

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摘要

This contribution describes our efforts in the design of a 130 nm CMOS ASIC that implements Skein, BLAKE, JH, Grostl, and Keccak, the five candidates selected by NIST in the third round SHA-3 competition. The objective of the ASIC is to accurately measure the performance and power dissipation of each candidate when implemented as an ASIC. The design of this ASIC, and its optimization for benchmarking, creates unique problems, related to the integration of five heterogeneous architectures on a single chip. We implemented each algorithm in a separate clock region, and we integrated an on-chip clock generator with flexible testing modes. The chip is further designed to be compatible with SASEBO-R board, a power-analysis and side-channel analysis environment. We report the design flow and test results of the chip, including area, performance and shmoo plot. Furthermore, we compare our ASIC benchmark with an equivalent FPGA benchmark.
机译：此贡献描述了我们在设计实现Skein，BLAKE，JH，Grostl和Keccak的130 nm CMOS ASIC方面所做的努力，这是NIST在第三回合SHA-3竞赛中选择的五名候选人。 ASIC的目标是在实现为ASIC时准确测量每个候选对象的性能和功耗。这种ASIC的设计及其基准测试的优化产生了与在单个芯片上集成五个异构体系结构有关的独特问题。我们在单独的时钟区域中实现每种算法，并集成了具有灵活测试模式的片上时钟发生器。该芯片还经过进一步设计，可与SASEBO-R板，功率分析和边通道分析环境兼容。我们报告了芯片的设计流程和测试结果，包括面积，性能和shmoo图。此外，我们将ASIC基准与等效的FPGA基准进行了比较。

著录项

  • 来源
    《Microprocessors and microsystems》 |2013年第2期|246-257|共12页
  • 作者

    Meeta Srivastav; Xu Guo; Sinan Huang; Dinesh Ganta; Michael B. Henry; Leyla Nazhandali; Patrick Schaumont;

  • 作者单位

    Center for Embedded Systems for Critical Applications (CESCAs), Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA 24061, United States;

    Center for Embedded Systems for Critical Applications (CESCAs), Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA 24061, United States;

    Center for Embedded Systems for Critical Applications (CESCAs), Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA 24061, United States;

    Center for Embedded Systems for Critical Applications (CESCAs), Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA 24061, United States;

    Center for Embedded Systems for Critical Applications (CESCAs), Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA 24061, United States;

    Center for Embedded Systems for Critical Applications (CESCAs), Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA 24061, United States;

    Center for Embedded Systems for Critical Applications (CESCAs), Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA 24061, United States;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Hash algorithm (HASH); SHA-3 competition;

    机译：专用集成电路（ASIC）;现场可编程门阵列（FPGA）;哈希算法（HASH）;SHA-3比赛;

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