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A dynamic adaptive converter and management for PRAM-based main memory

机译：基于PRAM的主存储器的动态自适应转换器和管理

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摘要

As DRAM-based main memory becomes a dominant factor in the energy consumption and cost of any computer system, new non-volatile memory technologies have been proposed to replace DRAMs. For example, PRAM is emerged as a leading alternative for main memory technology. However, the access latency of PRAM is significantly slower than that of DRAM and an interfacing converter is required to at least partly alleviate this latency difference. The interfacing converter sits between PRAM-based main memory and the last level of cache memory. In this paper, we present a proposed dynamic adaptive converter and its management scheme for PRAM-based main memory. In addition to overcoming long access latency, it provides enhanced endurance. The adaptive converter is composed of an aggressive streaming buffer to make better use of spatial locality by dynamically varying fetch size, a write buffer to improve endurance limit, and an adaptive filtering buffer to better utilize temporal locality. Our experimental results show that we can reduce buffer miss rate by about 59%, compared with using a single buffer structure with same space. Our approach also hides PRAM access latency more effectively. It improves the number of superblocks pre-fetched from main memory by 25%. Therefore, the converter shows its effectiveness comparable to a case with larger buffer space, without expending the extra power.
机译：由于基于DRAM的主存储器已成为任何计算机系统的能耗和成本的主要因素，因此提出了新的非易失性存储器技术来替代DRAM。例如，PRAM成为主存储技术的领先替代产品。但是，PRAM的访问等待时间比DRAM慢得多，并且需要接口转换器来至少部分缓解这种等待时间差异。接口转换器位于基于PRAM的主存储器和高速缓存的最后一级之间。在本文中，我们提出了一种针对基于PRAM的主存储器提出的动态自适应转换器及其管理方案。除了克服长访问延迟外，它还提供了增强的耐用性。自适应转换器由积极的流式缓冲区（通过动态改变获取大小来更好地利用空间局部性），写缓冲区（以提高耐久极限）和自适应滤波缓冲区（以更好地利用时间局部性）组成。我们的实验结果表明，与使用具有相同空间的单个缓冲区结构相比，可以将缓冲区丢失率降低约59％。我们的方法还可以更有效地隐藏PRAM访问延迟。从主存储器预取的超级块数量提高了25％。因此，该转换器在不消耗额外功率的情况下显示了与具有较大缓冲空间的情况相当的有效性。

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