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首页> 外文期刊>Microprocessors and microsystems >Dynamic signal driving strategy based high speed and low powered dual edge triggered flip flop design used memory applications
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Dynamic signal driving strategy based high speed and low powered dual edge triggered flip flop design used memory applications

机译：基于动态信号驱动策略的高速低功耗双边触发触发器设计，用于存储器应用

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Power utilization assumes a massive part in any of the integrated circuits, and it's rundown as a stand-out amongst essential difficulties in the universal innovation guide into semiconductors. Generally in integrated circuit, flip-flop and clock distribution system consume a lot of energy since they make and utilize the most extreme number of internal transitions. In the clock distribution system, the clock signal circulates from a typical point to every one of the components that required for the circuit. However this capacity is more important to the synchronous framework, much consideration needs to provide for the attributes of these clock signals. In the sequential circuits, a clock distribution system spends a lot of power given the high operating frequency of high capacitance. An existing approach to reducing the limits of a clock signal is based on the quantity of clocked transistors. In this, an advanced procedure is proposed and evaluated by utilizing Dual-Edge Triggered Flip-Flop (DETFF) depends on the Dynamic Signal Driving (DSD) strategy. This DETFF is executed in sequential circuits that have been ordered using Tanner Electronic Design Automation (EDA) tool which is used to simulate and examine control by using Dynamic Signal Driving (DSD) strategy. The outcomes demonstrate that the total power utilization is decreased in sequential benchmark circuit design. A number of Flip flops have been designed by various technologies such as reducing area, delay, and power, but this proposed dynamic signal driving scheme can be used for any integrated circuit- that can be reduced to all these three parameters to give the best trade-off for a particular ASIC platform. (C) 2019 Elsevier B.V. All rights reserved.
机译：功率利用率在任何集成电路中都占据着很大的比例，并且它在半导体通用创新指南中的主要困难中脱颖而出。通常，在集成电路中，触发器和时钟分配系统消耗大量能量，因为它们进行并利用了最极端的内部转换。在时钟分配系统中，时钟信号从一个典型点循环到电路所需的每个组件。但是，这种能力对同步框架而言更为重要，需要为这些时钟信号的属性提供很多考虑。在顺序电路中，考虑到高电容的高工作频率，时钟分配系统会花费大量功率。减少时钟信号限制的现有方法是基于时钟晶体管的数量。在这种情况下，提出了一种先进的程序，并通过利用取决于动态信号驱动（DSD）策略的双沿触发触发器（DETFF）进行了评估。此DETFF在使用Tanner电子设计自动化（EDA）工具订购的顺序电路中执行，该工具用于通过使用动态信号驱动（DSD）策略来模拟和检查控制。结果表明，在顺序基准电路设计中，总功率利用率降低了。已经通过各种技术（例如减小面积，延迟和功耗）设计了许多触发器，但是该提议的动态信号驱动方案可用于任何集成电路，可将其缩减为所有这三个参数以提供最佳的交易。 -关闭特定的ASIC平台。 （C）2019 Elsevier B.V.保留所有权利。

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