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Design of reversible logic based full adder in current-mode logic circuits

机译：基于可逆逻辑的全模式逻辑电路设计的设计

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Demand of Very Large Scale Integration (VLSI) circuits with very high speed and low power are increased due to communication system's transmission speed increase. During computation, heat is dissipated by a traditional binary logic or logic gates. There will be one or more input and only one output in irreversible gates. Input cannot be reconstructed using those outputs. In low power VLSI, reversible logic is commonly preferred in recent days. Information is not lost in reversible gates and back computation is possible in reversible circuits with reduced power dissipation. Reversible full adder circuits are implemented in the previous work to optimize the design and speed of the circuits. Reversible logic gates like TSG, Peres, Feynman, Toffoli, Fredkin are mostly used for designing reversible circuits. However it does not produced a satisfactory result in terms of static power dissipation. In this proposed research work, reversible logic is implemented in the full adder of MOS Current-Mode Logic (MCML) to achieve high speed circuit design with reduced power consumption. In VLSI circuits, reliable performance and high speed operation is exhibited by a MCML when compared with CMOS logic family. Area and better power consumption can be produced implementing reversible logic in full adder of MCML. Minimum garbage output and constant inputs are used in reversible full adder. The experimental results shows that the proposed designed circuit achieves better performance compared with the existing reversible logic circuits such as Feynman gate based FA, Peres gate based FA, TSG based FA in terms of average power, static power dissipation, static current and area. (C) 2020 Elsevier B.V. All rights reserved.
机译：由于通信系统的传输速度增加，由于通信系统的传输速度增加，增加了具有非常高的速度和低功率的大规模集成（VLSI）电路的需求。在计算期间，通过传统的二进制逻辑或逻辑门来消散热量。将有一个或多个输入，只有一个不可逆门的输出。无法使用这些输出重建输入。在低功率VLSI中，最近几天通常优选可逆逻辑。信息在可逆栅栏中不会丢失，并且在可逆电路中可以降低功耗的可逆电路。可逆的完整加法器电路是在先前的工作中实现的，以优化电路的设计和速度。可逆逻辑门，如TSG，PERES，Feynman，Toffoli，Fredkin主要用于设计可逆电路。然而，就静态功耗而言，它不会产生令人满意的结果。在这项建议的研究工作中，可逆逻辑在MOS电流模式逻辑（MCML）的完整加法器中实现，实现了降低功耗的高速电路设计。在VLSI电路中，与CMOS逻辑系列相比，MCML展示了可靠的性能和高速操作。可以在MCML的完整加法中实现地区和更好的功耗，实现可逆逻辑。最小垃圾输出和恒定输入用于可逆的完整加法器。实验结果表明，与平均功率，静态功耗，静态功耗，静态电流和面积相比，所提出的设计电路与现有的可逆逻辑电路（如Feynman Gate）的FA，TSG为基础的FA。 （c）2020 Elsevier B.v.保留所有权利。

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