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Reconfigurable parallelized TCAM architecture based on enhanced static memory cell

机译：基于增强静态存储器单元的可重构并行化TCAM架构

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摘要

Associative memories with tristate-based web crawlers assume a vital job in systems administration switches. The hunt space requests of ternary associative memories applications are always rising. In any case, existing acknowledge where content addressable memories can enter door clusters gate arrays experience the ill effects of capacity wastefulness. The proposed idea introduces high speed search engines empowered and intertwined with many internal ports of static memory cell put together ternary associative memories structure comparing with FPGA, to accomplish an effective usage of static arrangement of memories. Previous versions of static memory cell's exploits answers for this renewable solution and also diminish maximizing expansion provided in this customary Ternary content addressable memory design specifications leading with rapid and enormous development of static memories on behalf of unique utilizing fell square Static memories called block random access memories (BRAMs) over the boards of FPGA. Nonetheless, best in class FPGAs which entitled as block RAM have a base profundity restriction, which confines the capacity productivity for ternary associative memories bits. Our proposed arrangement maintains a strategic distance from this restriction with a provision of uniting and linking the customary idea of ternary memories and its table split-ups as an alternative of partitioned squares which is so called arranged block RAMs, along these lines accomplishing associative and productive ternary CAM memory structure. The arrangement works as arrangement of basic double block memories which was planned as static memories of many input and output ports which utilizing higher parallelism, influencing speeder and vital inner clock recurrence for getting partial-squares leading to block random memories in unique individual framework cycle. Actualized this novel structure on a Virtuoso environment of version six field programmable gate array gadget. Contrasted and in the earlier versions of gate array ternary content memories plans, this strategy accomplishes speeding of two and half of its occasions faster execution of its memory unit cycle. (C) 2020 Elsevier B.V. All rights reserved.
机译：具有基于三特星的Web爬网的关联存储器在系统管理交换机中承担了重要作业。三元关联存储器应用程序的狩猎空间请求总是上升。在任何情况下，现有确认内容可寻址存储器可以进入门簇门阵列体验容量浪费的不良影响。该建议介绍了高速搜索引擎授权并与许多内部静态存储器单元的内部端口交织在一起与FPGA相比的三元关联存储器结构，以实现静态排列存储器的有效利用。以前版本的静态存储器单元的利用此可再生解决方案的答案，并在此常规三元内容可寻址内存设计规范中提供最大化的扩展，以代表独特的静态静态存储器的静态存储器的快速和巨大开发，静态静态存储器迅速，静态静态回忆（糟糕）在FPGA的董事会上。尽管如此，最佳的FPGA中最佳，其被标题为块RAM具有基础的强度限制，这限制了三元关联存储器位的容量生产力。我们拟议的安排维持从这种限制的战略距离，并在提供单位和将Ternary Memories的惯常概念及其表格分开作为被称为所谓的块RAM的替代方案，沿着这些线条实现了联想和生产力三元凸轮内存结构。该布置作为基本双块存储器的布置，该存储器被计划为许多输入和输出端口的静态存储器，该输出端口利用更高的并行性，影响速度和重要内时钟复发，以获得部分正方形导致块在独特的单独框架周期中的随机存储器。实现了Vartuoso环境的六个字段可编程门阵列小工具的Virtuoso环境中的这种新结构。对比并在早期版本的门阵列三元内容存储器计划中，该策略实现了其内存单元周期的速度的两个和一半的超速。 （c）2020 Elsevier B.v.保留所有权利。

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