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首页> 美国政府科技报告 >Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having right and left ensembles of plural processors
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Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having right and left ensembles of plural processors

机译：用于机器人计算的高度并行可重新配置的计算机体系结构，具有多个处理器单元，每个处理器单元具有多个处理器的左右集合

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In a computer having a large number of single-instruction multiple data (SIMD) processors, each of the SIMD processors has two sets of three individual processor elements controlled by a master control unit and interconnected among a plurality of register file units where data is stored. The register files input and output data in synchronism with a minor cycle clock under control of two slave control units controlling the register file units connected to respective ones of the two sets of processor elements. Depending upon which ones of the register file units are enabled to store or transmit data during a particular minor clock cycle, the processor elements within an SIMD processor are connected in rings or in pipeline arrays, and may exchange data with the internal bus or with neighboring SIMD processors through interface units controlled by respective ones of the two slave control units.

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