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首页> 外文期刊>NEC Research & Development >Sub-1 V Supply Voltage GaAs LSI Technology Based on 0.25 μm E/D-HJFETs (IS~3Ts)
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Sub-1 V Supply Voltage GaAs LSI Technology Based on 0.25 μm E/D-HJFETs (IS~3Ts)

机译：基于0.25μmE / D-HJFET（IS〜3Ts）的低于1 V电源电压GaAs LSI技术

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摘要

An advantage of lowering the supply voltage for low-power consumption LSIs without sacrificing speed is described, based on switching analysis of an E/D-FET DCFL (Enhancement/Depletion-mode FET Direct-Coupled FET Logic) inverter. This analysis takes into account the effect of current voltage characteristics in the non-saturation regime. New technology of fabricating 0.25 μm gate E/D GaAs Heterojunction (HJ) FET LSIs, which has been developed as a step towards the development of ultra-low supply voltage LSIs, is also described. This technology, which is based upon all dry-process techniques, includes the formation of a 0.25 μm gate opening by optical lithography, and inner SiO_2 sidewalk. The f_(max) and g_(m max) for a Y-shaped gate E-HJFET fabricated by this technology are 108 GHz and 520 mS/mm, respectively. Excellent performance is also obtained with DCFL ring oscillators using n-AlGaAs/i-InGaAs pseudomorphic E/D-HJFETs. These include 18 ps/gate unloaded delay and 109 ps/gate loaded delay (FI = FO = 3, L = 1 mm) with 0.15 mW/gate at 0.6 V, where inverters have a sufficient noise margin of more than 180 mV. In addition, 10 Gbps error-free operation of a selector switch is demonstrated with 9.4 mW at 0.6 V.
机译：基于E / D-FET DCFL（增强/耗尽型FET直接耦合FET Logic）逆变器的开关分析，描述了在不牺牲速度的情况下降低低功耗LSI的电源电压的优势。该分析考虑了非饱和状态下电流电压特性的影响。还描述了制造0.25μm栅极E / D GaAs异质结（HJ）FET LSI的新技术，该新技术是朝着超低电源电压LSI的发展迈出的一步。该技术基于所有干法工艺，包括通过光刻技术形成0.25μm的栅极开口以及内部SiO_2人行道。通过此技术制造的Y形栅极E-HJFET的f_（max）和g_（m max）分别为108 GHz和520 mS / mm。使用n-AlGaAs / i-InGaAs伪形E / D-HJFET的DCFL环形振荡器也获得了出色的性能。其中包括18 ps /栅极的未加载延迟和109 ps /栅极的加载延迟（FI = FO = 3，L = 1 mm），在0.6 V时为0.15 mW /栅极，其中逆变器的噪声容限超过180 mV。此外，在0.6 V时以9.4 mW的功率演示了选择器开关的10 Gbps无误操作。

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