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首页> 外文期刊>Neurocomputing >A new scalable parallel adder based on spiking neural P systems, dendritic behavior, rules on the synapses and astrocyte-like control to compute multiple signed numbers
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A new scalable parallel adder based on spiking neural P systems, dendritic behavior, rules on the synapses and astrocyte-like control to compute multiple signed numbers

机译：一种新的可扩展并行加法器，基于尖峰神经P系统，树突行为，突触规则和类似星形胶质细胞的控制来计算多个有符号数

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This brief presents a scalable parallel neural adder circuit based on spiking neural P systems along with dendritic delays, dendritic feedback, rules on the synapses and astrocyte-like control to create a compact and highly scalable adder circuit. The proposed neural adder circuit adds multiple signed numbers either with few digits or with large number of digits in parallel employing a reduced number of neurons/synapses with simple and homogeneous spiking rules. The proposed neural adder was implemented in a DE0-Nano board (Altera Cyclone IV FPGA) to validate its performance. The results show that its implementation on a low-area low-cost FPGA requires small amount of circuitry. This potentially allows the development of highly parallel architectures that can be used in advanced applications, such as portable mobile robots, mobile devices, image and vision processing, among others. (c) 2018 Elsevier B.V. All rights reserved.
机译：本简介介绍了一种基于尖峰神经P系统的可扩展并行神经加法器电路，以及树突状延迟，树突反馈，突触规则和类似星形胶质细胞的控制，以创建紧凑且高度可扩展的加法器电路。所提出的神经加法器电路使用具有简单且均匀的尖峰规则的神经元/突触的数量减少，来并行地添加具有几个数字或具有多个数字的多个有符号数。所提出的神经加法器在DE0-Nano板（Altera Cyclone IV FPGA）中实现，以验证其性能。结果表明，其在低面积低成本FPGA上的实现需要少量电路。这潜在地允许开发高度并行的体系结构，该体系结构可用于高级应用程序，例如便携式移动机器人，移动设备，图像和视觉处理等。 （c）2018 Elsevier B.V.保留所有权利。

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