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首页> 外文期刊>IEEE Transactions on Parallel and Distributed Systems >Exploiting Locality in Sparse Matrix-Matrix Multiplication on Many-Core Architectures
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Exploiting Locality in Sparse Matrix-Matrix Multiplication on Many-Core Architectures

机译：在多核架构上利用稀疏矩阵-矩阵乘法的局部性

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摘要

Exploiting spatial and temporal localities is investigated for efficient row-by-row parallelization of general sparse matrix-matrix multiplication (SpGEMM) operation of the form C=AB on many-core architectures. Hypergraph and bipartite graph models are proposed for 1D rowwise partitioning of matrix A to evenly partition the work across threads with the objective of reducing the number of B -matrix words to be transferred from the memory and between different caches. A hypergraph model is proposed for B -matrix column reordering to exploit spatial locality in accessing entries of thread-private temporary arrays, which are used to accumulate results for C -matrix rows. A similarity graph model is proposed for B -matrix row reordering to increase temporal reuse of these accumulation array entries. The proposed models and methods are tested on a wide range of sparse matrices from real applications and the experiments were carried on a 60-core Intel Xeon Phi processor, as well as a two-socket Xeon processor. Results show the validity of the models and methods proposed for enhancing the locality in parallel SpGEMM operations.
机译：研究了利用空间和时间局部性来有效地对多核体系结构上的C = AB形式的通用稀疏矩阵-矩阵乘法（SpGEMM）操作进行逐行并行化。提出了超图和二部图模型用于矩阵A的一维行分区，以跨线程均匀地划分工作，目的是减少要从内存和不同缓存之间传输的B矩阵字的数量。提出了一种用于B矩阵列重排的超图模型，以利用空间局部性来访问线程专用临时数组的条目，这些线程用于累积C矩阵行的结果。提出了一种相似图模型用于B矩阵行重排序，以增加这些累积数组项的时间重用。所提出的模型和方法在实际应用中的各种稀疏矩阵上进行了测试，并且实验在60核Intel Xeon Phi处理器以及两路Xeon处理器上进行。结果表明，提出的用于在并行SpGEMM运算中增强局部性的模型和方法的有效性。

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