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Analog and RF Interference Mitigation for Integrated MIMO Receiver Arrays

机译：集成MIMO接收器阵列的模拟和RF干扰缓解

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摘要

Over the past decade, we have witnessed the maturation of silicon-based phased array technology, which has started to make an impact on commercial and military wireless applications. Over the next decade, driven by the development of next-generation wireless communication networks, we will see the maturation and impact of large-scale multiple-input–multiple-output (MIMO) technology. MIMO receiver arrays exploit digital array signal processing, and consequently are exposed to interference in the analog and radio-frequency (RF) front ends. The absence of analog/RF interference mitigation in traditional digital MIMO receiver arrays results in designs with high-dynamic-range and power-hungry analog and RF receiver front ends and analog-to-digital converters. This paper describes recently developed techniques for spatio–spectral interference mitigation in the analog and RF domain for digital MIMO receivers. The techniques proposed are flexible; tunable across operating frequency; scalable; present low cost, size, and power consumption overheads; and are experimentally validated through a 0.1–1.7-GHz four-element receiver front-end array integrated circuit (IC) prototype in 65-nm complementary metal–oxide–semiconductor (CMOS) technology.
机译：在过去的十年中，我们目睹了基于硅的相控阵技术的成熟，该技术已开始对商业和军事无线应用产生影响。在接下来的十年中，随着下一代无线通信网络的发展，我们将看到大规模多输入多输出（MIMO）技术的成熟和影响。 MIMO接收器阵列利用数字阵列信号处理，因此会受到模拟和射频（RF）前端的干扰。传统数字MIMO接收器阵列中缺乏模拟/ RF干扰缓解功能，导致设计具有高动态范围和高功耗模拟和RF接收器前端以及模数转换器。本文介绍了最近开发的用于数字MIMO接收机在模拟和RF域中减轻空间频谱干扰的技术。提出的技术是灵活的。跨工作频率可调；可扩展当前的低成本，尺寸和功耗开销；并且已通过采用65 nm互补金属氧化物半导体（CMOS）技术的0.1–1.7 GHz四元素接收器前端阵列集成电路（IC）原型进行了实验验证。

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