...
  • 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>Proceedings of the IEEE >Nanoarchitectonics for Heterogeneous Integrated Nanosystems
【24h】

Nanoarchitectonics for Heterogeneous Integrated Nanosystems

机译：异构集成纳米系统的纳米建筑学

获取原文
获取原文并翻译 | 示例
           
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Based on projections of the International Roadmap for Semiconductors (ITRS), the continued scaling of complementary metal-oxide semiconductor (CMOS) devices will face severe technical challenges. Among the most critical are power dissipation and device-level variabilities that will make circuit design very difficult. Potential device-level solutions that take advantage of new functional materials, self-assembly processes, low dissipation nanoscale devices, and architectures that aim in sustaining Moore''s law beyond the ITRS are discussed in this paper. Two potential paths forward are clear at this point. One path is to continue increasing chip-scale functional throughput by looking at new functional materials at atomic and molecular levels for assembly into new low-power devices with different logic state variables that can better tolerate variabilities. Another distinct approach is to increase chip-scale functionality by exploiting the heterogeneous integration of materials, such as compound semiconductors on silicon as enabled by the unique features in nanoscale epitaxy and self-assembly on a common substrate. This paper will discuss some possible methods forward in maintaining scaled CMOS and going beyond the roadmap.
机译：根据国际半导体发展路线图（ITRS）的预测，互补金属氧化物半导体（CMOS）器件的持续规模化将面临严峻的技术挑战。最关键的是功耗和器件级可变性，这将使电路设计非常困难。本文讨论了利用新功能材料，自组装工艺，低耗散纳米级器件以及旨在维持摩尔定律超越ITRS的架构的潜在器件级解决方案。在这一点上，有两条潜在的前进道路很明确。一种途径是通过在原子和分子水平上寻找新的功能材料以组装成具有不同逻辑状态变量的新低功耗设备来继续提高芯片级功能吞吐量，这些低逻辑设备可以更好地容忍可变性。另一种独特的方法是通过利用材料的异质集成来增加芯片规模的功能，例如硅上的化合物半导体，这是由于纳米级外延的独特功能以及在公共基板上的自组装所致。本文将讨论一些可行的方法，这些方法将在保持缩放的CMOS和超越路线图方面向前发展。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号