Recent advances in VLSI layout

Kuh E.S.; Ohtsuki T.

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Recent advances in VLSI layout

机译：VLSI布局的最新进展

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The current status of VLSI layout and directions for future research are addressed, with emphasis on the authors' own work. Necessary terminology and definitions and, whenever possible, a precise formulation of the problems are provided. Placement and floorplanning for both the sea-of-gates and building-block designs are examined. The former emphasizes the connectivity specification, whereas the latter must also consider module shape and size. Global routing based on a method of successive cuts on a chip is discussed. This is a hierarchical top-down approach that is useful for both of the above designs. A two-dimensional detailed routing problem and the rip-up and rerouting problem are also discussed. The field of computational geometry and its application to layout-in particular, to gridless routing and compaction-are reviewed, and layout engines are considered.

机译：着重介绍了VLSI布局的现状和未来研究的方向，重点是作者自己的工作。提供必要的术语和定义，并在可能的情况下提供对问题的精确表述。对门海和积木设计的布局和布局进行了检查。前者强调连接规范，而后者也必须考虑模块的形状和尺寸。讨论了基于芯片上连续切割方法的全局布线。这是一种分层的自顶向下方法，对上述两种设计都有用。还讨论了二维详细路由问题以及翻录和重路由问题。回顾了计算几何学领域及其在布局中的应用，特别是在无网格布线和压实中的应用，并考虑了布局引擎。

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来源
《Proceedings of the IEEE》 |1990年第2期|P.237-263|共27页
作者
Kuh E.S.; Ohtsuki T.;
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作者单位

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA;

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原文格式 PDF
正文语种 eng
中图分类一般性问题;无线电电子学、电信技术;
关键词
VLSI; circuit layout CAD; logic arrays; VLSI layout; advances in VLSI layout; building-block designs; compaction; computational geometry; connectivity specification; definitions; floorplanning; future research; global routing; gridless routing; hierarchical top-down approach; layout engines; method of successive cuts; module shape; placement; rip-up and rerouting problem; sea-of-gates; size; status; terminology; two-dimensional detailed routing problem;

机译：VLSI;电路布局CAD;逻辑阵列;VLSI布局;VLSI布局的先进性;构建模块设计;紧凑性;计算几何形状;连接性规范;定义;平面规划;未来研究;全局布线;无网格布线;分层自上而下的方法;布局发动机;连续切割的方法;模块形状;位置;撕裂和重新布线问题;门海;尺寸;状态;术语;二维详细布线问题;

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5. Analog/RF VLSI layout generation: Layout retargeting via symbolic template. [D] . Jangkrajarng, Nuttorn. 2006

机译：模拟/ RF VLSI布局生成：通过符号模板重新布局。
6. A study of the layout planning of plant facility based on the timed Petri net and systematic layout planning [O] . Hanwen Liu, Xiaobing Liu, Lin Lin, 2020

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7. The Recursive Grid Layout Scheme for VLSI Layout of Hierarchical Networks [O] . Chi-hsiang Yeh, Behrooz Parhami, Emmanouel A. Varvarigos 1999

机译：分层网络的VLSI布局的递归网格布局方案
8. Prolog for VLSI Layout: Experiences in the Design and Implementation of Topolog, A Prolog Based Module Generation and Layout System [R] . McGeer, P. C., Bush, W. R., Cheng, G., 1987

机译：VLsI布局的prolog：Topolog的设计和实现经验，基于prolog的模块生成和布局系统

Recent advances in VLSI layout

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