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首页> 外文期刊>Running algorithm of simulator of wireless distributed measurement-control system with rule based processing >Synthesis of multiple-valued logic networks for FPGA implementation using developmental genetic programming
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Synthesis of multiple-valued logic networks for FPGA implementation using developmental genetic programming

机译:使用发展型遗传编程综合用于FPGA实现的多值逻辑网络

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摘要

This paper presents a method of FPGA-oriented synthesis of multiple-valued logical networks. A multiple-valued network consists of modules connected by multivalued signals. During synthesis the modules are decomposed into smaller ones. For this purpose the symbolic decomposition is applied. Since the decomposition of modules strongly depends on the encoding of multiple-valued inputs and outputs, the result of synthesis depends on the order, in which the consecutive modules are implemented. Experimental results showed that our approach significantly reduces the cost of implementation.
机译:本文提出了一种面向FPGA的多值逻辑网络综合方法。多值网络由通过多值信号连接的模块组成。在合成期间,模块分解为较小的模块。为此,应用符号分解。由于模块的分解在很大程度上取决于多值输入和输出的编码,因此合成的结果取决于实现连续模块的顺序。实验结果表明,我们的方法大大降低了实施成本。

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