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Advanced CMOS device technologies for 45 nm node and below

机译：适用于45 nm及以下节点的先进CMOS器件技术

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摘要

We review and discuss the latest developments and technology options for 45 nm node and below, with scaled planar bulk MOSFETs and MuGFETs as emerging devices. One of the main metal gate (MG) candidates for scaled CMOS technologies are fully silicided (FUSI) gates. In this work, by means of a selective and controlled poly etch-back integration process, dual work-function Ni-based FUSI/HfSiON CMOS circuits with record ring oscillator performance (high-V_T) are reported (17 ps at V_(DD) = 1.1 V and 20 pA/μm I_(off)), meeting the ITRS 45 nm node requirement for low-power (LP) CMOS. Compatibility of FUSI and other MG with known stress boosters like stressed CESL (contact-etch-stop-layer with high intrinsic stress) or embedded SiGe in the pMOS S/D regions is validated. To obtain MuGFET devices that are competitive, as compared to conventional planar bulk devices, and that meet the stringent drive and leakage current requirements for the 32 nm node and beyond, higher channel mobilities are required. Results obtained by several strain engineering methods are presented here.
机译：我们回顾和讨论45纳米及以下节点的最新发展和技术选择，并以规模化的平面体MOSFET和MuGFET作为新兴器件。大规模CMOS技术的主要金属栅极（MG）候选之一是全硅化（FUSI）栅极。在这项工作中，通过选择性和受控的多晶硅回蚀集成工艺，报告了具有记录环形振荡器性能（高V_T）的双功函镍基FUSI / HfSiON CMOS电路（V_（DD）为17 ps） = 1.1 V和20 pA /μmI_（off）），满足ITRS 45 nm节点对低功耗（LP）CMOS的要求。验证了FUSI和其他MG与已知应力增强剂（如应力CESL（具有高固有应力的接触蚀刻停止层））或在pMOS S / D区域中嵌入SiGe的兼容性。为了获得与传统的平面体器件相比具有竞争力的MuGFET器件，并且满足32 nm节点及以后的严格驱动和泄漏电流要求，需要更高的沟道迁移率。这里介绍了通过几种应变工程方法获得的结果。

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