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An Efficient Architecture for Modified Lifting‑Based Discrete Wavelet Transform

机译：基于修改的升降的离散小波变换的高效架构

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摘要

A high speed and memory efficient lifting based architecture for one-dimensional (1-D) and two-dimensional (2-D) discrete wavelet transform (DWT) is proposed in this paper. The lifting algorithm is modified in this work to achieve a critical path of one multiplier delay with minimum pipeline registers. A 1-D DWT structure with two-input/two-output and four-input/four-output is developed based on the modified lifting scheme. The proposed 2-D DWT architecture for the Daubechies 5/3 and 9/7 filter comprises of two 1-D processors, together with a transpose and a temporal memory. An efficient transpose block is presented, which utilizes three registers to transpose the output sequence of the 1-D DWT block. The transpose block is independent of the size of the image read for the transform. The scanning process of an N × N image for a one-level 2-D transform is in Z fashion to minimize the temporal buffer to 4N and 2N for the 9/7 and 5/3 mode DWT respectively. The comparison results show that the proposed structure is hardware cost-effective and memory efficient, which is favorable for real-time visual operations. The model is described in VHDL and synthesized using the Cadence tool in 90 nm technology.
机译：本文提出了一种高速和记忆高效的基于一维（1-D）和二维（2-D）离散小波变换（DWT）的高效提升架构。在该工作中修改了提升算法，以实现具有最小管道寄存器的一个乘法器延迟的临界路径。基于改进的提升方案开发了具有两输入/两输出和四输入/四输出的1-D DWT结构。用于Daubechies 5/3和9/7滤波器的所提出的2-D DWT架构包括两个1-D处理器，以及转置和时间记忆。提出了一种有效的转置块，其利用三个寄存器转换1-D DWT块的输出序列。转置块与用于变换的图像的大小无关。用于单级2-D变换的N×N图像的扫描过程是以Z的方式，以分别最小化9/7和5/3模式DWT的时间缓冲器至4N和2N。比较结果表明，所提出的结构是硬件成本效益和内存高效，这有利于实时视觉操作。该模型在VHDL中描述并在90nm技术中使用Cadence工具合成。

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