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首页> 外文期刊>IEEE sensors journal >A Low-Power/Low-Noise Readout Circuit for Integrated Capacitive Sensors
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A Low-Power/Low-Noise Readout Circuit for Integrated Capacitive Sensors

机译:用于集成电容传感器的低功耗/低噪声读出电路

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摘要

A switched-capacitor integrated system is presented in this work that attains sub-fF measurement resolution in integrated capacitive sensors, with 1.5-kHz bandwidth and 50-(mu)W average power consumption in continuous function mode. The proposed design employs a pair of nonoverlapping clocks and an operational transconductance amplifier (OTA) that can be made as simple as a basic differential pair. The system exhibits 0.8percent linearity error and 0.01 fF/(deg C) temperature drift. It is appropriate for differential, absolute, and ratiometric capacitance measurements, and shows robustness against interconnection parasitics, transistor dimensional mismatch, and process variations, which are an important feature in the case of sensor-die CMOS postprocessing.
机译:在这项工作中提出了一种开关电容器集成系统,该系统在集成电容传感器中达到了低于fF的测量分辨率,在连续功能模式下具有1.5kHz的带宽和50μW的平均功耗。所提出的设计采用一对不重叠的时钟和一个运算跨导放大器(OTA),该放大器可以像基本差分对一样简单。该系统表现出0.8%的线性误差和0.01 fF /(℃)的温度漂移。它适用于差分,绝对和比例电容测量,并显示出抗互连寄生性,晶体管尺寸失配和工艺变化的鲁棒性,这在传感器芯片CMOS后处理的情况下是重要特征。

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