An 8 ns 4 Mb serial access memory

Kuriyama H.; Hirose T.

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An 8 ns 4 Mb serial access memory

机译：一个8 ns 4 Mb串行访问存储器

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摘要

A new architecture for serial access memory is described that enables a static random access memory (SRAM) to operate in a serial access mode. The design target is to access all memory address serially from any starting address with an access time of less than 10 ns. This can be done by all initializing procedure and three new circuit techniques. The initializing procedure is introduced to start the serial operation at an arbitrary memory address. Three circuit techniques eliminate extra delay time caused by an internal addressing of column lines, sense amplifiers, word lines, and memory cell blocks. This architecture was successfully implemented in a 4-Mb CMOS SRAM using a 0.6 mu m CMOS process technology. The measured serial access time was 8 ns at a single power supply voltage of 3.3 V.

机译：描述了一种用于串行访问存储器的新体系结构，该体系结构使静态随机访问存储器（SRAM）能够在串行访问模式下运行。设计目标是从任何起始地址开始以小于10 ns的访问时间串行访问所有存储器地址。这可以通过所有初始化过程和三种新的电路技术来完成。引入了初始化过程以在任意存储器地址处开始串行操作。三种电路技术消除了由列线，读出放大器，字线和存储单元模块的内部寻址引起的额外延迟时间。使用0.6μmCMOS工艺技术在4-Mb CMOS SRAM中成功实现了该体系结构。在3.3 V的单电源电压下，测得的串行访问时间为8 ns。

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来源
《IEEE Journal of Solid-State Circuits》 |1991年第4期|P.502-506|共5页
作者
Kuriyama H.; Hirose T.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
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1. 100-MHz serial access architecture for 4-Mb field memory [J] . Miyauchi M., Ikeda H. IEEE Journal of Solid-State Circuits . 1991,第4期

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2. Normally-off type nonvolatile static random access memory with perpendicular spin torque transfer-magnetic random access memory cells and smallest number of transistors [J] . Chika Tanaka, Keiko Abe, Hiroki Noguchi, Japanese journal of applied physics . 2014,第4S期

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3. The contribution to immediate serial recall of rehearsal, search speed, access to lexical memory, and phonological coding: An investigation at the construct level [J] . Tehan G, Fogarty G, Ryan K Memory & cognition . 2004,第5期

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4. 100 MHz serial access architecture for 4 Mb field memory [C] . Ikeda, H., Tsujimoto, . 1990

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5. Serial Code Accelerators for Heterogeneous Multi-core Processor with Three-Dimensional Stacked Memory. [D] . Jacob, Philip. 2010

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6. Serial Position Markers in Space: Visuospatial Priming of Serial Order Working Memory Retrieval [O] . Maya De Belder, Elger Abrahamse, Mauro Kerckhof, 2015

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7. Recall of accessible items from memory as a function of executive instructions, delay tasks, and serial position [O] . Bert Zippel 1980

机译：从内存中召回可访问的项目作为执行指令，延迟任务和串行位置的函数

An 8 ns 4 Mb serial access memory

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